Advertisement
MN102L62GGY (IC401) : Unit CPU
Pin function
Symbol
I/O
Pin No.
1
Micon wait signal input
I
WAIT
2
Read enable
RE
O
3
Spindle muting output to IC251
O
SPMUTE
4
Write enable
WEN
O
5
HD Type selection
O
HDTYPE
6
Chip select for ODC
O
CS1
7
Chip select for ZIVA
CS2
O
8
Chip select for outer ROM
O
CS3
9
Driver mute
DRVMUTE
O
10
Short brake terminal
O
SBRK
11
LSI reset
O
LSIRST
12
Bus selection input
WORD
I
13
Address bus 0 for CPU
O
A0
14
Address bus 1 for CPU
A1
O
15
Address bus 2 for CPU
O
A2
16
Address bus 3 for CPU
O
A3
17
Power supply
VDD
-
18
Non connect
-
SYSCLK
19
Ground
VSS
-
20
Not use (Connect to vss)
-
XI
21
Non connect
-
XO
22
Power supply
VDD
-
23
Clock signal input(13.5MHz)
I
OSCI
24
Clock signal output(13.5MHz)
OSCO
O
25
CPU Mode selection input
I
MODE
26
O
Address bus 4 for CPU
A4
27
Address bus 5 for CPU
O
A5
28
Address bus 6 for CPU
O
A6
29
Address bus 7 for CPU
A7
O
30
Address bus 8 for CPU
O
A8
31
Address bus 9 for CPU
A9
O
32
Address bus 10 for CPU
O
A10
33
Address bus 11 for CPU
O
A11
34
Power supply
VDD
-
35
Address bus 12 for CPU
O
A12
36
Address bus 13 for CPU
A13
O
37
Address bus 14 for CPU
O
A14
38
Address bus 15 for CPU
O
A15
39
Address bus 16 for CPU
A16
O
40
Address bus 17 for CPU
O
A17
41
Address bus 18 for CPU
A18
O
42
Address bus 19 for CPU
O
A19
43
Ground
-
VSS
44
Address bus 20 for CPU
A20
O
45
TX Select
O
TXSEL
46
Detection switch of traverse
TRVSW
I
inside
47
Connect to TP408
-
HUGUP
48
HFM Control output to Q103
HFMON
O
49
Connect to pick-up
O
HAGUP
50
Connect to TP407
-
-
Function
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
I/O
Connect to TP406
-
-
Connect to TP405
-
-
Connect to TP404
-
P85/TM5IO
Power supply
VDD
-
Connect to TP403
-
-
Serial enable signal for FEP
O
FEPEN
Standby signal for FEP
SLEEP
O
Connect to TP402
-
-
Communication busy
BUSY
I
Communication request
O
REQ
Ground
-
VSS
EEPROM chip select
EPCS
O
EEPROM clock
O
EPSK
EEPROM data input
EPDI
I
EEPROM data output
O
EPDO
Power supply
-
VDD
Communication clock
SCLKO
O
Communication input data
I
S2UDT
Communication output data
U2SDT
O
Clock for ADSC serial
O
CPSCK
Not use (Pull down)
I
P74/SBI1
ADSC serial data output
SDOUT
O
Not use (Pull up)
I
-
Not use (Pull up)
-
I
NMI Terminal
I
NMI
Interrupt input of ADSC
I
ADSCIRQ
Interrupt input of ODC
ODCIRQ
I
Interrupt input of ZIVA
I
DECIRQ
Not use (Pull down)
CSSIRQ
I
Interruption of system control
I
ODCIRQ2
Address data selection input
I
ADSEP
Reset input
I
RST
Power supply
-
VDD
Test signal 1 input
TEST1
I
Test signal 2 input
I
TEST2
Test signal 3 input
TEST3
I
Test signal 4 input
I
TEST4
Test signal 5 input
I
TEST5
Test signal 6 input
TEST6
I
Test signal 7 input
I
TEST7
Test signal 8 input
TEST8
I
Ground
-
VSS
Data bus 0 of CPU
I/O
D0
Data bus 1 of CPU
D1
I/O
Data bus 2 of CPU
I/O
D2
Data bus 3 of CPU
D3
I/O
Data bus 4 of CPU
I/O
D4
Data bus 5 of CPU
I/O
D5
Data bus 6 of CPU
D6
I/O
Data bus 7 of CPU
I/O
D7
XV-LTR1
Function
1-29
Advertisement
