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3.13.4.4 Superfilter
The superfilter is an active filter that provides a low-noise supply for the VCOs, receiver and
transmitter injection amplifiers. Regulator U0950, located in the controller section, supplies 9.3 Vdc
to the FGU section thru the filtering network consisting of L6755, C6806, C6807, and C6818. This
voltage is applied to pin 30 (SFIN) of U6751 and the emitter of Q6759. The output is a superfiltered
8.2 Vdc at the junction of pin 28 (SFOUT) of U6751 and the collector of Q6759. Filtering is
accomplished with capacitors C6808, C6790, and C6791 at the output of this circuit and C6775 at
pin 26 of U6751.
3.13.4.5 Modulation
To support many voice, data, and signaling protocols, XTL 1500 radios must modulate the
transmitter carrier frequency over a wide audio-frequency range, from less than 10 Hz up to more
than 6 kHz. The LV Frac-N IC supports audio frequencies down to zero Hz by using dual-port
modulation. The audio signal at pin 10 (MODIN) is internally divided into high- and low-frequency
components, which modulate both the synthesizer dividers and the external VCOs through signal
MODOUT (pin 41). The IC is adjusted to achieve flat modulation frequency response during
transmitter modulation balance calibration using a built-in modulation attenuator.
The Digital-to-Analog Converter (DAC) IC (U0900), and switched-capacitor filter (SCF) IC (FL0900)
form the interface between the radio's DSP and the analog input of the LV Frac-N IC.
3.13.4.6 Charge Pump Bias
External circuitry connected to pin 39 (Bias 2) and pin 40 (Bias 1) of U6751 determine the current
that is applied to the charge-pump circuitry. During receive mode, resistors R6768, R6769, and
R6766 set the current supplied to pin 40 (Bias 1). Transistor Q6757 and resistors R6763, R6762,
and capacitor C6795 form a circuit that momentarily increases the current to pin 40 (Bias 1) during
receiver programming of U6751. This circuit is activated by pin 46 (ADAPTSW) of U6751 during the
transition of programming U6751 to frequency and effectively decreases the length of time for the
synthesizer to lock on frequency. Similarly, during transmitter mode, resistors R6768, R6769, and
R6768 set the current supplied to pin 39 (Bias 2). Transistor Q6758 and resistors R6770, R6767,
and capacitor C6794 form a circuit that momentarily increases the current to pin 39 (Bias 2) during
transmitter programming of U6751.
3.13.4.7 Loop Filter
The loop filter operates in synchronization with the phase detector of U6751 in two modes, normal
and adapt. In normal mode, the loop filter forms a third-order loop filter consisting of components
R6764, R6765, R6761, C6776 to C6779, and C6785 to C6789.
Pin 43 (IOUT) of U6751 provides the charge-pump current for steering of the control voltage line to
the VCOs. During normal mode, pin 45 (IADAPT) is set to a high impedance and has no effect on the
loop filter. When U6751 is programmed to a new frequency, the IC is initially operated in adapt mode.
In this mode the loop filter is reconfigured for a wider bandwidth allowing the synthesizer to lock
faster. The charge-pump output is supplied through pin 45 (IADAPT) in this mode, and this
reconfigures the loop filter to behave like a second-order filter.
3.13.4.8 Lock Detect
Lock status of the synthesizer loop is provided to the microprocessor by pin 4 (LOCK) of U6751. A
high level (3.0 Vdc) indicates that the loop is stable. A low voltage indicates that the loop is not
locked and will result in a Fail 001 to be displayed on the control head display.
June 15, 2005
Theory of Operation: Frequency Generation Unit (FGU)
6815854H01-A
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