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Philips Semiconductors
Universal asynchronous receiver/transmitter (UART)
AC ELECTRICAL CHARACTERISTICS
SYMBOL
SYMBOL
Reset timing (Figure 3)
t
Reset pulse width
RES
5
Bus timing (Figure 4)
t
A0–A2 setup time to RDN, WRN low
AS
t
A0–A2 hold time from RDN, WRN low
AH
t
CEN setup time to RDN, WRN low
CS
t
CEN hold time from RDN, WRN high
CH
t
WRN, RDN pulse width
RW
t
Data valid after RDN low
DD
t
Data bus floating after RDN high
DF
t
Data setup time before WRN high
DS
t
Data hold time after WRN high
DH
t
Time between reads and/or writes
RWD
MPI and MPO timing (Figure 5)
t
MPI input setup time before RDN low
PS
t
MI input hold time after RDN low
PH
t
MPO output valid after WRN high
PD
Interrupt timing (Figure 6)
t
INTRN negated
IR
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY, TxEMT interrupt)
Reset command (break change interrupt)
Reset command (MPI change interrupt)
Stop C/T command (counter interrupt)
Write IMR (clear of interrupt mask bit)
Clock timing (Figure 7)
t
X1/CLK high or low time
CLK
9
f
X1/CLK frequency
CLK
t
Counter/timer clock high or low time
CTC
8
f
Counter/timer clock frequency
CTC
t
RxC high or low time
RX
8
f
RxC frequency (16X)
RX
RxC frequency (1X)
t
TxC high or low time
TX
TxC frequency (16X)
8
f
TX
TxC frequency (1X)
Transmitter timing (Figure 8)
t
TxD output delay from TxC external clock input on IP pin
TXD
t
Output delay from TxC low at OP pin to TxD data output
TCS
Receiver timing (Figure 9)
t
RxD data setup time before RxC high at external clock input on IP pin
RXS
t
RxD data hold time after RxC high at external clock input on IP pin
RXH
NOTES:
1. Parameters are valid over specified temp. range. See Ordering Information table for applicable operating temp. and V
2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of
20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
output voltages of 0.8V and 2V as appropriate.
3. Typical values are at +25 C, typical supply voltages, and typical processing parameters.
4. Test condition for outputs: C
L
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the 'strobing' input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RDN (also CEN and WRN) are ORed inter-
nally. As a consequence, this signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. If CEN is used as the 'strobing' input, this parameter defines the minimum high time between one CEN and the next. The RDN signal must
be negated for t
guarantee that any status register changes are valid.
RWD
7. Consecutive write operations to the command register require at least three rising edges of the X1 clock between writes.
8. These parameters are guaranteed by design, but are not 100% tested in production.
9. Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
2006 Aug 04
1, 2, 3, 4
PARAMETER
PARAMETER
6, 7
5
= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C
LIMITS
Min
100
10
100
0
0
150
50
30
150
30
30
100
0
100
0
220
0
3.6864
0
220
0
0
0
100
100
6
Product data sheet
SCC2691
UNIT
UNIT
Typ
Max
ns
ns
ns
ns
ns
ns
125
ns
110
ns
ns
ns
ns
ns
ns
370
ns
370
ns
370
ns
370
ns
370
ns
370
ns
270
ns
ns
4.0
MHz
ns
4.0
MHz
ns
2.0
MHz
1.0
MHz
ns
2.0
MHz
1.0
MHz
350
ns
150
ns
ns
ns
supply range.
CC
= 50pF, R
= 2.7k
to V
.
L
L
CC
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