2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal,
V
, to a point 0.5V above V
. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment
M
OL
are pronounced and can greatly affect the resultant measurement.
t
CLK
t
CTC
t
Rx
t
Tx
X1/CLK
C/T CLK
RxC
TxC
DRIVING
FROM EXTERNAL
SOURCE
CLK
5V
470
N/C
2006 Aug 04
t
PH
Figure 5. I/O Timing
1
1
Figure 6. Interrupt Timing
t
CLK
t
CTC
t
Rx
t
Tx
X1
X2
Figure 7. Clock Timing
t
PD
V
M
t
IR
V
OL
t
IR
V
+0.5V
OL
Y1 = 3.6864MHz, C
C1 = C2 = 24pF
C1
C2
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY. . . . . . . . . . . . . . 2–4MHz
LOAD CAPACITANCE (C
). . . 20 or 32pF (typical)
L
TYPE OF OPERATION . . . . . .PARALLEL RESONANT, FUND. MODE