Sony MDS-JE510 Service Manual page 46

• IC121 Digital Signal Processor, Digital Servo Signal Processor, EFM/ACIRC Encoder/Decoder,
Shock-proof Memory Controller, ATRAC Encoder/Decoder, 2M Bit DRAM (CXD2650R or CXD2652AR)
Pin No. Pin Name
1 MNT0 (FOK)
MNT1 (SHCK)
2
MNT2 (XBUSY)
3
MNT3 (SLOC)
4
5 SWDT
SCLK
6
XLAT
7
SRDT
8
SENS
9
10 XRST
SQSY
11
DQSY
12
13 RECP
XINT
14
TX
15
OSCI
16
OSCO
17
18 XTSL
DVDD
19
DVSS
20
DIN
21
DOUT
22
ADDT
23
DADT
24
LRCK
25
XBCK
26
FS256
27
DVDD
28
A03 to A00
29 to 32
A10
33
A04 to A08
34 to 38
A11
39
DVSS
40
XOE
41
42 XCAS
A09
43
XRAS
44
XWE
45
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
I/O
FOK signal output to the system control
O
"H" is output when focus is on
Track jump detection signal output to the system control
O
Monitor 2 output to the system control
O
Monitor 3 output to the system control
O
I Writing data signal input from the system control
Serial clock signal input from the system control
I (S)
Serial latch signal input from the system control
I (S)
Reading data signal output to the system control
O (3)
Internal status (SENSE) output to the system control
O (3)
I (S) Reset signal input from the system control "L": Reset
Subcode Q sync (SCOR) output to the system control
O
"L" is output every 13.3 msec. Almost all, "H" is output
Digital In U-bit CD format subcode Q sync (SCOR) output to the system control
O
"L" is output every 13.3 msec Almost all, "H" is output
I Laser power switching input from the system control "H": Recording, "L": Playback
Interrupt status output to the system control
O
Recording data output enable input from the system control
I
System clock input (512Fs=22.5792 MHz)
I
System clock output (512Fs=22.5792 MHz) (Not used)
O
I System clock frequency setting "L": 45.1584 MHz, "H": 22.5792 MHz (Fixed at "H")
+3V power supply (Digital)
—
Ground (Digital)
—
Digital audio input (Optical input)
I
Digital audio output (Optical output)
O
I Data input from the A/D converter
Data output to the D/A converter
O
LR clock output for the A/D and D/A converter (44.1 kHz)
O
Bit clock output to the A/D and D/A converter (2.8224 MHz)
O
11.2896 MHz clock output (Not used)
O
+3V power supply (Digital)
—
O
O
DRAM address output (Used : CXD2652AR, Not used : CXD2650R)
O
O
Ground (Digital)
—
Output enable output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
O
CAS signal output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
O
Address output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
O
RAS signal output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
O
Write enable signal output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
O
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Function