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7-5 DVD Data Processor
7-5-1 Outline
SIC1(S5L1455) performs Sync detection, EFM demodulation and error correction and Spindle motor control (CLV
control) after inputting sliced EFM signal of RF signal at disc playback and EFM read clock (PLCK) signal generat-
ed from PLL. Outputs data which converted to the last audio and video from A/V decoder (ZIC1). SIC1 uses exter-
nal memory(4M DRAM) as buffer as well as for error correction and carries out Variable Bit Rate transfer function.
VBR function uses the external buffer as buffer to absorb the difference of transfer rate occurring because the trans-
fer rate of disc playback is faster than data transfer rate demanded by A/V decoder (Video/Audio Signal Process
Chip).
In case of general disc refresh, the memory is almost filled up periodically. It is because Write rate to memory after
disc playback and signal process is faster than Read of A/V decoder. When the memory is filled, this status is report-
ed by interrupt to main micom, which controls the servo to kick back the pick-up to the previous track after mem-
orizing the last data read from disc until now. It takes some times to jump to the previous track and return to the
original(jump location) again. The memory will have an empty space because A/V decoder reads out data of mem-
ory.
When the memory has an empty space, where data can be processed and written and the pick-up correctly gets to
the original location(before kick back location) again, it reads data again avoids the interrupt of data read previ-
ously. The basic operation repeats to perform as described above.
7-5-2 Block Diagram
FOD
SIC3
TRD
(FAN8728)
SLD
SPD
Motor Driver
VREF
D(15..0)
SIC2
A(8..0)
4Mbit
/RAS
/LCAS
EDO
/UCAS
/WE
DRAM
/OE
Samsung Electronics
RIC1
(S5L1463)
RF IC
SIC1
(S5L1455)
Digital Servo
&
DSP
/DSPCS
/RD
/WD
MEMAD0
MEMDA(7..0)
33.8688MHz
FOKB
RFO
27MHz
16.9344MHz
STROBE
REQUEST
DACK
SDATA(7..0)
DVDSOS
ERROR
SENSE
SLOCK
DSPWAIT
DSPIRQ
RSTB
/FLASHCS
/DSPCS
/RD
/WD
MEMAD(19..0)
MEMAD(15..0)
/FLASHCS
/RD
ZIC3
/WD
Flash Memory
MEMAD(19..0)
8Mbit
MEMDA(15..0)
Fig. 7-17
Circuit Operating Descriptions
ZIC2
64Mbit
SDRAM
SCL
SDA
ZIC1
(Vaddis 5E)
MPEG Decoder
&
CPU
SRQ
SCLK
RXD
TXD
RRQ
27MHz
ZIC7
2Kbit
2
E PROM
FIC1
(GMS81C2020)
Front Panel
Controller
7-13
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