Page 1 MSP430x4xx Family User’s Guide 2007 Mixed Signal Products SLAU056G...
Page 3 Read This First About This Manual This manual discusses modules and peripherals of the MSP430x4xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices.
Page 4 Glossary Glossary ACLK Auxiliary Clock See Basic Clock Module Analog-to-Digital Converter Brown-Out Reset See System Resets, Interrupts, and Operating Modes Bootstrap Loader See www.ti.com/msp430 for application reports Central Processing Unit See RISC 16-Bit CPU Digital-to-Analog Converter Digitally Controlled Oscillator See FLL+ Module Destination See RISC 16-Bit CPU Frequency Locked Loop...
Page 5 Register Bit Conventions Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition Bit Accessibility Read/write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1...
Page 7: Table Of Contents
Contents Contents Introduction ..............Architecture .
Page 8 Contents RISC 16-Bit CPU ..............CPU Introduction .
Page 9 Contents FLL+ Clock Module ............. . FLL+ Clock Module Introduction .
Page 10 Contents 32-Bit Hardware Multiplier ............32-Bit Hardware Multiplier Introduction .
Page 11 Contents 12 Watchdog Timer, Watchdog Timer+ ..........12-1 12.1 Watchdog Timer Introduction .
Page 12 Contents 16 Timer_B ............... 16-1 16.1 Timer_B Introduction .
Page 13 Contents 19 Universal Serial Communication Interface, UART Mode ......19-1 19.1 USCI Overview ............19-2 19.2 USCI Introduction: UART Mode .
Page 14 Contents 22 OA ................22-1 22.1 OA Introduction .
Page 15 Contents 25 LCD_A Controller ............. . . 25-1 25.1 LCD_A Controller Introduction .
Page 16 Contents 28 SD16_A ............... . 28-1 28.1 SD16_A Introduction .
Page 17: Introduction
Chapter 1 Introduction This chapter describes the architecture of the MSP430. Topic Page Architecture ..........Flexible Clock System .
Page 18: Architecture
(MAB) and memory data bus (MDB). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x4xx family include: Ultralow-power architecture extends battery life 0.1-μA RAM retention 0.8-μA real-time clock mode...
Page 19: Embedded Emulation
Embedded Emulation Figure 1−1. MSP430 Architecture Clock ACLK Flash/ Peripheral Peripheral Peripheral System SMCLK MCLK MAB 16-Bit RISC CPU 16-Bit MDB 16-Bit MDB 8-Bit Conv. JTAG ACLK SMCLK Peripheral Peripheral Peripheral Watchdog Peripheral 1.3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources.
Page 20: Address Space
Address Space 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1−2. See the device-specific data sheets for specific memory maps. Code access are always performed on even addresses. Data can be accessed as bytes or words.
Page 21: Ram
Address Space 1.4.2 RAM starts at 0200h. The end address of RAM depends on the amount of RAM present and varies by device. RAM can be used for both code and data. 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules.
Page 22 Address Space Figure 1−3. Bits, Bytes, and Words in a Byte Organized Memory xxxAh . . Bits . . xxx9h . . Bits . . xxx8h Byte xxx7h Byte xxx6h Word (High Byte) xxx5h xxx4h Word (Low Byte) xxx3h Introduction...
Page 23: System Resets, Interrupts, And Operating Modes
Chapter 2 System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x4xx system resets, interrupts, and operating modes. Topic Page System Reset and Initialization ....... . . Interrupts .
Page 24: System Reset And Initialization
System Reset and Initialization 2.1 System Reset and Initialization The system reset circuitry shown in Figure 2−1 sources both a power-on reset (POR) and a power-up clear (PUC) signal. Different events trigger these reset signals and different initial conditions exist depending on which signal was generated.
Page 25: Brownout Reset (Bor)
System Reset and Initialization 2.1.1 Brownout Reset (BOR) All MSP430x4xx devices have a brownout reset circuit. The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the V terminal. The brownout reset circuit resets the device by triggering a POR signal when power is applied or removed.
Page 26: Device Initial Conditions After System Reset
System Reset and Initialization 2.1.2 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: The RST/NMI pin is configured in the reset mode. I/O pins are switched to input mode as described in the Digital I/O chapter. Other peripheral modules and registers are initialized as described in their respective chapters in this manual.
Page 27: Interrupts
System Reset and Initialization 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2−3. The nearer a module is to the CPU/NMIRS, the higher the priority. Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously.
Page 28: Non)-Maskable Interrupts (Nmi)
System Reset and Initialization 2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enable bit (GIE), but are enabled by individual interrupt enable bits (ACCVIE, NMIIE, OFIE). When a NMI interrupt is accepted, all NMI interrupt enable bits are automatically reset.
Page 29 System Reset and Initialization Figure 2−4. Block Diagram of (Non)-Maskable Interrupt Sources ACCV ACCVIFG FCTL3.2 ACCVIE IE1.5 Clear Flash Module RST/NMI KEYV SVS_POR System Reset Generator NMIIFG NMIRS IFG1.4 WDTTMSEL Clear WDTNMIES WDTNMI WDTQn NMIIE WDTIFG IE1.4 Clear IFG1.0 Clear Counter OSCFault OFIFG...
Page 30 System Reset and Initialization Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator. The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit. The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault.
Page 31: Maskable Interrupts
System Reset and Initialization Example of an NMI Interrupt Handler The NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMI service routine resets the interrupt flags and re-enables the interrupt-enable bits according to the application needs as shown in Figure 2−5.
Page 32 System Reset and Initialization 2.2.3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)-maskable interrupts to be requested.
Page 33 System Reset and Initialization Return From Interrupt The interrupt handling routine terminates with the instruction: (return from an interrupt service routine) RETI The return from the interrupt takes 5 cycles to execute the following actions and is illustrated in Figure 2−7. 1) The SR with all previous settings pops from the stack.
Page 34: Interrupt Vectors
System Reset and Initialization 2.2.4 Interrupt Vectors The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h as described in Table 2−1. A vector is programmed by the user with the 16-bit address of the corresponding interrupt service routine.
Page 35: Operating Modes
Operating Modes 2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 2−9. The operating modes take into account three different needs: Ultralow-power Speed and data throughput Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2−8.
Page 36 Operating Modes Figure 2−9. MSP430x4xx Operating Modes For FLL+ Clock System RST/NMI Reset Active WDT Active, WDTIFG = 0 Time Expired, Overflow WDTIFG = 1 RST/NMI is Reset Pin WDTIFG = 1 WDT is Active RST/NMI WDT Active, NMI Active Security Key Violation Active Mode CPU Is Active...
Page 37: Entering And Exiting Low-Power Modes
Operating Modes 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes. The program flow is: Enter interrupt service routine: The PC and SR are stored on the stack The CPUOFF, SCG1, and OSCOFF bits are automatically reset Options for returning from the interrupt service routine: The original SR is popped from the stack, restoring the previous operating mode.
Page 38: Principles For Low-Power Applications
Principles for Low Power Applications 2.4 Principles for Low Power Applications Often, the most important factor for reducing power consumption is using the MSP430’s clock system to maximize the time in LPM3. LPM3 power consumption is less than 2 μA typical with both a real-time clock function and all interrupts active.
Page 39: Risc 16-Bit Cpu
Chapter 3 RISC 16-Bit CPU This chapter describes the MSP430 CPU, addressing modes, and instruction set. Topic Page CPU Introduction ..........CPU Registers .
Page 40: Cpu Introduction
CPU Introduction 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The CPU can address the complete address range without paging. The CPU features include: RISC architecture with 27 instructions and 7 addressing modes Orthogonal architecture with every instruction usable with every...
Page 41 CPU Introduction Figure 3−1. CPU Block Diagram MDB − Memory Data Bus Memory Address Bus − MAB R0/PC Program Counter R1/SP Stack Pointer R2/SR/CG1 Status R3/CG2 Constant Generator General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose...
Page 42: Cpu Registers
CPU Registers 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 have dedicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to be executed.
Page 43: Stack Pointer (Sp)
CPU Registers 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes.
Page 44: Status Register (Sr)
CPU Registers 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remain- ing combinations of addressing modes are used to support the constant gen- erator.
Page 45: Constant Generator Registers Cg1 And Cg2
CPU Registers 3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constants are selected with the source-register addressing modes (As), as described in Table 3−2.
Page 46: General-Purpose Registers R4 To R15
CPU Registers 3.2.5 General-Purpose Registers R4 to R15 The twelve registers, R4 to R15, are general-purpose registers. All of these registers can be used as data registers, address pointers, or index values, and they can be accessed with byte or word instructions as shown in Figure 3−7. Figure 3−7.
Page 47: Addressing Modes
Addressing Modes 3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in Table 3−3 describe the contents of the As (source) and Ad (destination) mode bits.
Page 48: Register Mode
Addressing Modes 3.3.1 Register Mode The register mode is described in Table 3−4. Table 3−4. Register Mode Description Assembler Code Content of ROM R10,R11 R10,R11 Length: One or two words Operation: Move the content of R10 to R11. R10 is not affected. Comment: Valid for source and destination Example:...
Page 49: Indexed Mode
Addressing Modes 3.3.2 Indexed Mode The indexed mode is described in Table 3−5. Table 3−5. Indexed Mode Description Assembler Code Content of ROM 2(R5),6(R6) X(R5),Y(R6) X = 2 Y = 6 Length: Two or three words Operation: Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6).
Page 50: Symbolic Mode
Addressing Modes 3.3.3 Symbolic Mode The symbolic mode is described in Table 3−6. Table 3−6. Symbolic Mode Description Assembler Code Content of ROM MOV EDE,TONI X(PC),Y(PC) X = EDE − PC Y = TONI − PC Length: Two or three words Operation: Move the contents of the source address EDE (contents of PC + X) to the destination address TONI (contents of PC + Y).
Page 51: Absolute Mode
Addressing Modes 3.3.4 Absolute Mode The absolute mode is described in Table 3−7. Table 3−7. Absolute Mode Description Assembler Code Content of ROM &EDE,&TONI X(0),Y(0) X = EDE Y = TONI Length: Two or three words Operation: Move the contents of the source address EDE to the destination address TONI.
Page 52: Indirect Register Mode
Addressing Modes 3.3.5 Indirect Register Mode The indirect register mode is described in Table 3−8. Table 3−8. Indirect Mode Description Assembler Code Content of ROM @R10,0(R11) @R10,0(R11) Length: One or two words Operation: Move the contents of the source address (contents of R10) to the destination address (contents of R11).
Page 53: Indirect Autoincrement Mode
Addressing Modes 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 3−9. Table 3−9. Indirect Autoincrement Mode Description Assembler Code Content of ROM @R10+,0(R11) @R10+,0(R11) Length: One or two words Operation: Move the contents of the source address (contents of R10) to the destination address (contents of R11).
Page 54: Immediate Mode
Addressing Modes 3.3.7 Immediate Mode The immediate mode is described in Table 3−10. Table 3−10.Immediate Mode Description Assembler Code Content of ROM #45h,TONI MOV @PC+,X(PC) X = TONI − PC Length: Two or three words It is one word less if a constant of CG1 or CG2 can be used. Operation: Move the immediate constant 45h, which is contained in the word following the instruction, to destination address TONI.
Page 55: Instruction Set
Instruction Set 3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions. The core instructions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automatically by the assembler with an equivalent core instruction.
Page 56: Double-Operand (Format I) Instructions
Instruction Set 3.4.1 Double-Operand (Format I) Instructions Figure 3−9 illustrates the double-operand instruction format. Figure 3−9. Double Operand Instruction Format S-Reg D-Reg Op-code Table 3−11 lists and describes the double operand instructions. Table 3−11. Double Operand Instructions Mnemonic S-Reg, Operation Status Bits D-Reg src →...
Page 57: Single-Operand (Format Ii) Instructions
Instruction Set 3.4.2 Single-Operand (Format II) Instructions Figure 3−10 illustrates the single-operand instruction format. Figure 3−10. Single Operand Instruction Format Op-code D/S-Reg Table 3−12 lists and describes the single operand instructions. Table 3−12.Single Operand Instructions Mnemonic S-Reg, Operation Status Bits D Reg D-Reg →...
Page 58: Jumps
Instruction Set 3.4.3 Jumps Figure 3−11 shows the conditional-jump instruction format. Figure 3−11. Jump Instruction Format Op-code 10-Bit PC Offset Table 3−13 lists and describes the jump instructions. Table 3−13.Jump Instructions Mnemonic S-Reg, D-Reg Operation Jump to label if zero bit is set JEQ/JZ Label Jump to label if zero bit is reset...
Page 59 Instruction Set * ADC[.W] Add carry to destination * ADC.B Add carry to destination Syntax ADC.W ADC.B Operation dst + C −> dst Emulation ADDC #0,dst ADDC.B #0,dst Description The carry bit (C) is added to the destination operand. The previous contents of the destination are lost.
Page 60 Instruction Set ADD[.W] Add source to destination ADD.B Add source to destination Syntax src,dst ADD.W src,dst ADD.B src,dst Operation src + dst −> dst Description The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise...
Page 61 Instruction Set ADDC[.W] Add source and carry to destination ADDC.B Add source and carry to destination Syntax ADDC src,dst ADDC.W src,dst ADDC.B src,dst Operation src + dst + C −> dst Description The source operand and the carry bit (C) are added to the destination operand. The source operand is not affected.
Page 62 Instruction Set AND[.W] Source AND destination AND.B Source AND destination Syntax src,dst or AND.W src,dst AND.B src,dst Operation src .AND. dst −> dst Description The source operand and the destination operand are logically ANDed. The result is placed into the destination. Status Bits N: Set if result MSB is set, reset if not set Z: Set if result is zero, reset otherwise...
Page 63 Instruction Set BIC[.W] Clear bits in destination BIC.B Clear bits in destination Syntax src,dst or BIC.W src,dst BIC.B src,dst Operation .NOT.src .AND. dst −> dst Description The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected.
Page 64 Instruction Set BIS[.W] Set bits in destination BIS.B Set bits in destination Syntax src,dst or BIS.W src,dst BIS.B src,dst Operation src .OR. dst −> dst Description The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Status Bits Status bits are not affected.
Page 65 Instruction Set BIT[.W] Test bits in destination BIT.B Test bits in destination Syntax src,dst or BIT.W src,dst Operation src .AND. dst Description The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected. Status Bits N: Set if MSB of result is set, reset otherwise Z: Set if result is zero, reset otherwise...
Page 66 Instruction Set * BR, BRANCH Branch to ..destination Syntax Operation dst −> PC Emulation dst,PC Description An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used. The branch instruction is a word instruction.
Page 67 Instruction Set CALL Subroutine Syntax CALL Operation −> tmp dst is evaluated and stored SP − 2 −> SP −> @SP PC updated to TOS −> PC dst saved to PC Description A subroutine call is made to an address anywhere in the 64K address space. All addressing modes can be used.
Page 68 Instruction Set * CLR[.W] Clear destination * CLR.B Clear destination Syntax or CLR.W dst CLR.B Operation 0 −> dst Emulation #0,dst MOV.B #0,dst Description The destination operand is cleared. Status Bits Status bits are not affected. Example RAM word TONI is cleared. TONI ;...
Page 69 Instruction Set * CLRC Clear carry bit Syntax CLRC Operation 0 −> C Emulation #1,SR Description The carry bit (C) is cleared. The clear carry instruction is a word instruction. Status Bits N: Not affected Z: Not affected C: Cleared V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Page 70 Instruction Set * CLRN Clear negative bit Syntax CLRN 0 → N Operation (.NOT.src .AND. dst −> dst) Emulation #4,SR Description The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction.
Page 71 Instruction Set * CLRZ Clear zero bit Syntax CLRZ 0 → Z Operation (.NOT.src .AND. dst −> dst) Emulation #2,SR Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction.
Page 72 Instruction Set CMP[.W] Compare source and destination CMP.B Compare source and destination Syntax src,dst CMP.W src,dst CMP.B src,dst Operation dst + .NOT.src + 1 (dst − src) Description The source operand is subtracted from the destination operand. This is accomplished by adding the 1s complement of the source operand plus 1. The two operands are not affected and the result is not stored;...
Page 73 Instruction Set * DADC[.W] Add carry decimally to destination * DADC.B Add carry decimally to destination Syntax DADC DADC.W src,dst DADC.B Operation dst + C −> dst (decimally) Emulation DADD #0,dst DADD.B #0,dst Description The carry bit (C) is added decimally to the destination. Status Bits N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise...
Page 74 Instruction Set DADD[.W] Source and carry added decimally to destination DADD.B Source and carry added decimally to destination Syntax DADD src,dst or DADD.W src,dst DADD.B src,dst Operation src + dst + C −> dst (decimally) Description The source operand and the destination operand are treated as four binary coded decimals (BCD) with positive signs.
Page 75 Instruction Set * DEC[.W] Decrement destination * DEC.B Decrement destination Syntax DEC.W DEC.B Operation dst − 1 −> dst Emulation #1,dst Emulation SUB.B #1,dst Description The destination operand is decremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset.
Page 76 Instruction Set * DECD[.W] Double-decrement destination * DECD.B Double-decrement destination Syntax DECD DECD.W DECD.B Operation dst − 2 −> dst Emulation #2,dst Emulation SUB.B #2,dst Description The destination operand is decremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise...
Page 77 Instruction Set * DINT Disable (general) interrupts Syntax DINT 0 → GIE Operation (0FFF7h .AND. SR → SR .NOT.src .AND. dst −> dst) Emulation #8,SR Description All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR.
Page 78 Instruction Set * EINT Enable (general) interrupts Syntax EINT 1 → GIE Operation (0008h .OR. SR −> SR / .src .OR. dst −> dst) Emulation #8,SR Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR.
Page 79 Instruction Set * INC[.W Increment destination * INC.B Increment destination Syntax or INC.W dst INC.B Operation dst + 1 −> dst Emulation #1,dst Description The destination operand is incremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise...
Page 80 Instruction Set * INCD[.W] Double-increment destination * INCD.B Double-increment destination Syntax INCD or INCD.W INCD.B Operation dst + 2 −> dst Emulation #2,dst Emulation ADD.B #2,dst Example The destination operand is incremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise...
Page 81 Instruction Set * INV[.W] Invert destination * INV.B Invert destination Syntax INV.B Operation .NOT.dst −> dst Emulation #0FFFFh,dst Emulation XOR.B #0FFh,dst Description The destination operand is inverted. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT.
Page 82 Instruction Set Jump if carry set Jump if higher or same Syntax label label If C = 1: PC + 2 × offset −> PC Operation If C = 0: execute following instruction Description The status register carry bit (C) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 83 Instruction Set JEQ, JZ Jump if equal, jump if zero Syntax label, label If Z = 1: PC + 2 × offset −> PC Operation If Z = 0: execute following instruction Description The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 84 Instruction Set Jump if greater or equal Syntax label If (N .XOR. V) = 0 then jump to label: PC + 2 × offset −> PC Operation If (N .XOR. V) = 1 then execute the following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If both N and V are set or reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 85 Instruction Set Jump if less Syntax label If (N .XOR. V) = 1 then jump to label: PC + 2 × offset −> PC Operation If (N .XOR. V) = 0 then execute following instruction Description The status register negative bit (N) and overflow bit (V) are tested. If only one is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 86 Instruction Set Jump unconditionally Syntax label PC + 2 × offset −> PC Operation Description The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status Bits Status bits are not affected. Hint: This one-word instruction replaces the BRANCH instruction in the range of −511 to +512 words relative to the current program counter.
Page 87 Instruction Set Jump if negative Syntax label if N = 1: PC + 2 × offset −> PC Operation if N = 0: execute following instruction Description The negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 88 Instruction Set Jump if carry not set Jump if lower Syntax label label if C = 0: PC + 2 × offset −> PC Operation if C = 1: execute following instruction Description The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 89 Instruction Set Jump if not equal Jump if not zero Syntax label label If Z = 0: PC + 2 × offset −> PC Operation If Z = 1: execute following instruction Description The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter.
Page 90 Instruction Set MOV[.W] Move source to destination MOV.B Move source to destination Syntax src,dst MOV.W src,dst MOV.B src,dst Operation src −> dst Description The source operand is moved to the destination. The source operand is not affected. The previous contents of the destination are lost.
Page 91 Instruction Set * NOP No operation Syntax Operation None Emulation #0, R3 Description No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status Bits Status bits are not affected. The NOP instruction is mainly used for two purposes: To fill one, two, or three memory words To adjust software timing...
Page 92 Instruction Set * POP[.W] Pop word from stack to destination * POP.B Pop byte from stack to destination Syntax POP.B Operation @SP −> temp SP + 2 −> SP temp −> dst Emulation @SP+,dst MOV.W @SP+,dst Emulation MOV.B @SP+,dst Description The stack location pointed to by the stack pointer (TOS) is moved to the destination.
Page 93 Instruction Set PUSH[.W] Push word onto stack PUSH.B Push byte onto stack Syntax PUSH PUSH.W PUSH.B SP − 2 → SP Operation src → @SP Description The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS). Status Bits Status bits are not affected.
Page 94 Instruction Set * RET Return from subroutine Syntax Operation @SP→ PC SP + 2 → SP Emulation @SP+,PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call.
Page 95 Instruction Set RETI Return from interrupt Syntax RETI → SR Operation → SP SP + 2 → PC → SP SP + 2 Description The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two.
Page 96 Instruction Set * RLA[.W] Rotate left arithmetically * RLA.B Rotate left arithmetically Syntax RLA.W RLA.B Operation C <− MSB <− MSB−1 ..LSB+1 <− LSB <− 0 Emulation dst,dst ADD.B dst,dst Description The destination operand is shifted left one position as shown in Figure 3−14. The MSB is shifted into the carry bit (C) and the LSB is filled with 0.
Page 97 Instruction Set * RLC[.W] Rotate left through carry * RLC.B Rotate left through carry Syntax RLC.W RLC.B Operation C <− MSB <− MSB−1 ..LSB+1 <− LSB <− C Emulation ADDC dst,dst Description The destination operand is shifted left one position as shown in Figure 3−15. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C).
Page 98 Instruction Set RRA[.W] Rotate right arithmetically RRA.B Rotate right arithmetically Syntax RRA.W RRA.B Operation MSB −> MSB, MSB −> MSB−1, ... LSB+1 −> LSB, LSB −> C Description The destination operand is shifted right one position as shown in Figure 3−16. The MSB is shifted into the MSB, the MSB is shifted into the MSB−1, and the LSB+1 is shifted into the LSB.
Page 99 Instruction Set RRC[.W] Rotate right through carry RRC.B Rotate right through carry Syntax RRC.W Operation C −> MSB −> MSB−1 ..LSB+1 −> LSB −> C Description The destination operand is shifted right one position as shown in Figure 3−17. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C).
Page 100 Instruction Set * SBC[.W] Subtract source and borrow/.NOT. carry from destination * SBC.B Subtract source and borrow/.NOT. carry from destination Syntax SBC.W SBC.B Operation dst + 0FFFFh + C −> dst dst + 0FFh + C −> dst Emulation SUBC #0,dst SUBC.B #0,dst...
Page 101 Instruction Set * SETC Set carry bit Syntax SETC Operation 1 −> C Emulation #1,SR Description The carry bit (C) is set. Status Bits N: Not affected Z: Not affected C: Set V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example Emulation of the decimal subtraction: Subtract R5 from R6 decimally...
Page 102 Instruction Set * SETN Set negative bit Syntax SETN Operation 1 −> N Emulation #4,SR Description The negative bit (N) is set. Status Bits N: Set Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. 3-64 RISC 16-Bit CPU...
Page 103 Instruction Set * SETZ Set zero bit Syntax SETZ Operation 1 −> Z Emulation #2,SR Description The zero bit (Z) is set. Status Bits N: Not affected Z: Set C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. RISC 16-Bit CPU 3-65...
Page 104 Instruction Set SUB[.W] Subtract source from destination SUB.B Subtract source from destination Syntax src,dst SUB.W src,dst SUB.B src,dst Operation dst + .NOT.src + 1 −> dst [(dst − src −> dst)] Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the constant 1.
Page 105 Instruction Set SUBC[.W]SBB[.W] Subtract source and borrow/.NOT. carry from destination SUBC.B,SBB.B Subtract source and borrow/.NOT. carry from destination Syntax SUBC src,dst SUBC.W src,dst src,dst SBB.W src,dst SUBC.B src,dst SBB.B src,dst Operation dst + .NOT.src + C −> dst (dst − src − 1 + C −> dst) Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the carry bit (C).
Page 106 Instruction Set SWPB Swap bytes Syntax SWPB Operation Bits 15 to 8 <−> bits 7 to 0 Description The destination operand high and low bytes are exchanged as shown in Figure 3−18. Status Bits Status bits are not affected. Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Page 107 Instruction Set Extend Sign Syntax Operation Bit 7 −> Bit 8 ..Bit 15 Description The sign of the low byte is extended into the high byte as shown in Figure 3−19. Status Bits N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT.
Page 108 Instruction Set * TST[.W] Test destination * TST.B Test destination Syntax or TST.W dst TST.B Operation dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation #0,dst CMP.B #0,dst Description The destination operand is compared with zero. The status bits are set accord- ing to the result.
Page 109 Instruction Set XOR[.W] Exclusive OR of source with destination XOR.B Exclusive OR of source with destination Syntax src,dst XOR.W src,dst XOR.B src,dst Operation src .XOR. dst −> dst Description The source and destination operands are exclusive ORed. The result is placed into the destination.
Page 110: Instruction Cycles And Lengths
Instruction Set 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK. Interrupt and Reset Cycles Table 3−14 lists the CPU cycles for interrupt overhead and reset.
Page 111 Instruction Set Format-I (Double Operand) Instruction Cycles and Lengths Table 3−16 lists the length and CPU cycles for all addressing modes of format-I instructions. Table 3−16.Format I Instruction Cycles and Lengths Addressing Mode No. of Length of Cycles Instruction Example R5,R8 x(Rm) R5,4(R6)
Page 112: Instruction Set Description
Instruction Set 3.4.5 Instruction Set Description The instruction map is shown in Figure 3−20 and the complete instruction set is summarized in Table 3−17. Figure 3−20. Core Instruction Map 0xxx 4xxx 8xxx Cxxx 1xxx RRC.B SWPB RRA.B PUSH PUSH.B CALL RETI 14xx 18xx...
Page 113 Instruction Set Table 3−17.MSP430 Instruction Set Mnemonic Description dst + C → dst † Add C to destination ADC(.B) src + dst → dst Add source to destination ADD(.B) src,dst src + dst + C → dst Add source and C to destination ADDC(.B) src,dst src .and.
Page 114 3-76 RISC 16-Bit CPU...
Page 115: 16-Bit Msp430X Cpu
Chapter 4 16-Bit MSP430X CPU This chapter describes the extended MSP430X 16-bit RISC CPU with 1-MB memory access, its addressing modes, and instruction set. The MSP430X CPU is implemented in all MSP430 devices that exceed 64-KB of address space. Topic Page CPU Introduction .
Page 116: Cpu Introduction
CPU Introduction 4.1 CPU Introduction The MSP430X CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The MSP430X CPU can address a 1-MB address range without paging. In addition, the MSP430X CPU has fewer interrupt overhead cycles and fewer instruction cycles in some cases than the MSP430 CPU, while maintaining the same or better code density than the MSP430 CPU.
Page 117: Cpu Introduction
CPU Introduction Figure 4−1. MSP430X CPU Block Diagram MDB − Memory Data Bus Memory Address Bus − MAB 16 15 R0/PC Program Counter R1/SP Pointer Stack R2/SR Status Register R3/CG2 Constant Generator General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose...
Page 118: Interrupts
Interrupts 4.2 Interrupts The MSP430X uses the same interrupt structure as the MSP430: Vectored interrupts with no polling necessary Interrupt vectors are located downward from address 0FFFEh Interrupt operation for both MSP430 and MSP430X CPUs is described in Chapter 2 System Resets, Interrupts, and Operating modes, Section 2 Interrupts.
Page 119: Cpu Registers
CPU Registers 4.3 CPU Registers The CPU incorporates sixteen registers R0 to R15. Registers R0, R1, R2, and R3 have dedicated functions. R4 to R15 are working registers for general use. 4.3.1 The Program Counter PC The 20-bit program counter (PC/R0) points to the next instruction to be executed.
Page 120 CPU Registers The program counter is automatically stored on the stack with CALL, or CALLA instructions, and during an interrupt service routine. Figure 4−4 shows the storage of the program counter with the return address after a CALLA instruction. A CALL instruction stores only bits 15:0 of the PC. Figure 4−4.
Page 121: Stack Pointer (Sp)
CPU Registers 4.3.2 Stack Pointer (SP) The 20-bit stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes.
Page 122 CPU Registers The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 4−8. Figure 4−8. PUSH SP - POP SP Sequence PUSH SP POP SP The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction.
Page 123: Status Register (Sr)
CPU Registers 4.3.3 Status Register (SR) The 16-bit status register (SR/R2), used as a source or destination register, can only be used in register mode addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator.
Page 124: Cpu Registers
CPU Registers Description Zero bit. This bit is set when the result of an operation is zero and cleared when the result is not zero. Carry bit. This bit is set when the result of an operation produced a carry and cleared when no carry occurred. 4-10 16-Bit MSP430X CPU...
Page 125: The Constant Generator Registers Cg1 And Cg2
CPU Registers 4.3.4 The Constant Generator Registers CG1 and CG2 Six commonly used constants are generated with the constant generator registers R2 (CG1) and R3 (CG2), without requiring an additional 16-bit word of program code. The constants are selected with the source register addressing modes (As), as described in Table 4−2.
Page 126: The General Purpose Registers R4 To R15
CPU Registers 4.3.5 The General Purpose Registers R4 to R15 The twelve CPU registers R4 to R15, contain 8-bit, 16-bit, or 20-bit values. Any byte-write to a CPU register clears bits 19:8. Any word-write to a register clears bits 19:16. The only exception is the SXT instruction. The SXT instruction extends the sign through the complete 20-bit register.
Page 127 CPU Registers Figure 4−11 and Figure 4−12 show 16-bit word handling (.W suffix). The handling is shown for a source register and a destination memory word and for a source memory word and a destination register. Figure 4−11. Register-Word Operation Register-Word Operation High Byte Low Byte...
Page 128 CPU Registers Figure 4−13 and Figure 4−14 show 20-bit address-word handling (.A suffix). The handling is shown for a source register and a destination memory address-word and for a source memory address-word and a destination register. Figure 4−13. Register − Address-Word Operation Register −...
Page 129: Addressing Modes
CPU Registers 4.4 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand use 16-bit or 20-bit addresses. The MSP430 and MSP430X instructions are usable throughout the entire 1-MB memory range. Table 4−3. Source/Destination Addressing As/Ad Addressing Mode Syntax...
Page 130: Register Mode
CPU Registers 4.4.1 Register Mode Operation: The operand is the 8-, 16-, or 20-bit content of the used CPU register. Length: One, two, or three words Comment: Valid for source and destination Byte operation: Byte operation reads only the 8 LSBs of the source register Rsrc and writes the result to the 8 LSBs of the destination register Rdst.
Page 131 CPU Registers Example: BISX.A R5,R6 ; This instruction logically ORs the 20-bit data contained in R5 with the 20-bit contents of R6. The extension word contains the A/L-bit for 20-bit data. The instruction word uses byte mode with bits A/L:B/W = 01. The result of the instruction is: Before: After: Address...
Page 132: Indexed Mode
CPU Registers 4.4.2 Indexed Mode The Indexed mode calculates the address of the operand by adding the signed index to a CPU register. The Indexed mode has three addressing possibilities: Indexed mode in lower 64-KB memory MSP430 instruction with Indexed mode addressing memory above the lower 64-KB memory.
Page 133 CPU Registers Example: ADD.B 1000h(R5),0F000h(R6); The previous instruction adds the 8-bit data contained in source byte 1000h(R5) and the destination byte 0F000h(R6) and places the result into the destination byte. Source and destination bytes are both located in the lower 64 KB due to the cleared bits 19:16 of registers R5 and R6.
Page 134 CPU Registers MSP430 Instruction with Indexed Mode in Upper Memory If the CPU register Rn points to an address above the lower 64-KB memory, the Rn bits 19:16 are used for the address calculation of the operand. The operand may be located in memory in the range Rn ±32 KB, because the index, X, is a signed 16-bit value.
Page 135 CPU Registers Length: Two or three words Operation: The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the CPU register Rn. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh.
Page 136 CPU Registers MSP430X Instruction with Indexed Mode When using an MSP430X instruction with Indexed mode, the operand can be located anywhere in the range of Rn ± 19 bits. Length: Three or four words Operation: The operand address is the sum of the 20-bit CPU register content and the 20-bit index.
Page 137 CPU Registers The extension word contains the MSBs of the source index and of the destination index and the A/L-bit for 20-bit data. The instruction word uses byte mode due to the 20-bit data length with bits A/L:B/W = 01. Before: After: Address...
Page 138 CPU Registers 4.4.3 Symbolic Mode The Symbolic mode calculates the address of the operand by adding the signed index to the program counter. The Symbolic mode has three addressing possibilities: Symbolic mode in lower 64-KB memory MSP430 instruction with symbolic mode addressing memory above the lower 64-KB memory.
Page 139 CPU Registers The previous instruction adds the 8-bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI. Bytes EDE and TONI and the program are located in the lower 64 KB. Source: Byte EDE located at address 0,579Ch, pointed to by PC + 4766h where the PC index 4766h is the result of 0579Ch −...
Page 140 CPU Registers MSP430 Instruction with Symbolic Mode in Upper Memory If the PC points to an address above the lower 64-KB memory, the PC bits 19:16 are used for the address calculation of the operand. The operand may be located in memory in the range PC ±32 KB, because the index, X, is a signed 16-bit value.
Page 141 CPU Registers Length: Two or three words Operation: The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the PC. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh.
Page 142 CPU Registers MSP430X Instruction with Symbolic Mode When using an MSP430X instruction with Symbolic mode, the operand can be located anywhere in the range of PC ± 19 bits. Length: Three or four words Operation: The operand address is the sum of the 20-bit PC and the 20-bit index.
Page 143: Absolute Mode
CPU Registers 4.4.4 Absolute Mode The Absolute mode uses the contents of the word following the instruction as the address of the operand. The Absolute mode has two addressing possibilities: Absolute mode in lower 64-KB memory MSP430X instruction with Absolute mode 16-Bit MSP430X CPU 4-29...
Page 144 CPU Registers Absolute Mode in Lower 64 KB If an MSP430 instruction is used with Absolute addressing mode, the absolute address is a 16-bit value and therefore points to an address in the lower 64 KB of the memory range. The address is calculated as an index from 0 and is stored in the word following the instruction The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications.
Page 145 CPU Registers MSP430X Instruction with Absolute Mode If an MSP430X instruction is used with Absolute addressing mode, the absolute address is a 20-bit value and therefore points to any address in the memory range. The address value is calculated as an index from 0. The four MSBs of the index are contained in the extension word, and the 16 LSBs are contained in the word following the instruction.
Page 146: Indirect Register Mode
CPU Registers 4.4.5 Indirect Register Mode The Indirect Register mode uses the contents of the CPU register Rsrc as the source operand. The Indirect Register mode always uses a 20-bit address. Length: One, two, or three words Operation: The operand is the content the addressed memory location. The source register Rsrc is not modified.
Page 147: Indirect, Autoincrement Mode
CPU Registers 4.4.6 Indirect, Autoincrement Mode The Indirect Autoincrement mode uses the contents of the CPU register Rsrc as the source operand. Rsrc is then automatically incremented by 1 for byte instructions, by 2 for word instructions, and by 4 for address-word instructions immediately after accessing the source operand.
Page 148: Immediate Mode
CPU Registers 4.4.7 Immediate Mode The Immediate mode allows accessing constants as operands by including the constant in the memory location following the instruction. The program counter PC is used with the Indirect Autoincrement mode. The PC points to the immediate value contained in the next word. After the fetching of the immediate operand, the PC is incremented by 2 for byte, word, or address-word instructions.
Page 149 CPU Registers MSP430X Instructions with Immediate Mode If an MSP430X instruction is used with immediate addressing mode, the constant is a 20-bit value. The 4 MSBs of the constant are stored in the extension word and the 16 LSBs of the constant are stored in the word following the instruction.
Page 150: Msp430 And Msp430X Instructions
MSP430 and MSP430X Instructions 4.5 MSP430 and MSP430X Instructions MSP430 instructions are the 27 implemented instructions of the MSP430 CPU. These instructions are used throughout the 1-MB memory range unless their 16-bit capability is exceeded. The MSP430X instructions are used when the addressing of the operands or the data length exceeds the 16-bit capability of the MSP430 instructions.
Page 151: Msp430 Instructions
MSP430 and MSP430X Instructions 4.5.1 MSP430 Instructions The MSP430 instructions can be used, regardless if the program resides in the lower 64 KB or beyond it. The only exceptions are the instructions CALL and RET which are limited to the lower 64 KB address range. CALLA and RETA instructions have been added to the MSP430X CPU to handle subroutines in the entire address range with no code size overhead.
Page 152 MSP430 and MSP430X Instructions Single Operand (Format II) Instructions Figure 4−23 shows the format for MSP430 single operand instructions, except RETI. The destination word is appended for the Indexed, Symbolic, Absolute and Immediate modes .Table 4−5 lists the seven single operand instructions. Figure 4−23.
Page 153 MSP430 and MSP430X Instructions Jumps Figure 4−24 shows the format for MSP430 and MSP430X jump instructions. The signed 10-bit word offset of the jump instruction is multiplied by two, sign-extended to a 20-bit address, and added to the 20-bit program counter. This allows jumps in a range of -511 to +512 words relative to the program counter in the full 20-bit address space Jumps do not affect the status bits.
Page 154 MSP430 and MSP430X Instructions Emulated Instructions In addition to the MSP430 and MSP430X instructions, emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves. Instead, they are replaced automatically by the assembler with a core instruction. There is no code or performance penalty for using emulated instructions.
Page 155 MSP430 and MSP430X Instructions MSP430 Instruction Execution The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to MCLK. Instruction Cycles and Length for Interrupt, Reset, and Subroutines Table 4−8 lists the length and the CPU cycles for reset, interrupts and subroutines.
Page 156 MSP430 and MSP430X Instructions Format-II (Single Operand) Instruction Cycles and Lengths Table 4−9 lists the length and the CPU cycles for all addressing modes of the MSP430 single operand instructions. Table 4−9. MSP430 Format-II Instruction Cycles and Length Length of No.
Page 157 MSP430 and MSP430X Instructions Format-I (Double Operand) Instruction Cycles and Lengths Table 4−10 lists the length and CPU cycles for all addressing modes of the MSP430 format-I instructions. Table 4−10.MSP430 Format-I Instructions Cycles and Length No. of Length of Addressing Mode Cycles Instruction Example...
Page 158: Msp430X Extended Instructions
MSP430X Extended Instructions 4.5.2 MSP430X Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space. Most MSP430X instructions require an additional word of op-code called the extension word. Some extended instructions do not require an additional word and are noted in the instruction description.
Page 159 MSP430X Extended Instructions Register Mode Extension Word The register mode extension word is shown in Figure 4−25 and described in Table 4−11. An example is shown in Figure 4−27. Figure 4−25. The Extension Word for Register Modes (n−1)/Rn 0001 Table 4−11. Description of the Extension Word Bits for Register Mode Description 15:11 Extension word op-code.
Page 160 MSP430X Extended Instructions Non-Register Mode Extension Word The extension word for non-register modes is shown in Figure 4−26 and described in Table 4−12. An example is shown in Figure 4−28. Figure 4−26. The Extension Word for Non-Register Modes Source bits 19:16 Destination bits 19:16 Table 4−12.Description of the Extension Word Bits for Non-Register Modes Description...
Page 161 MSP430X Extended Instructions Figure 4−27. Example for an Extended Register/Register Instruction Rsvd (n−1)/Rn Op-code Rsrc Rdst XORX.A R9,R8 1: Repetition count in bits 3:0 0: Use Carry 01: Address word 14(XOR) 8(R8) XORX instruction Source R9 Destination R8 Destination register mode Source register mode Figure 4−28.
Page 162 MSP430X Extended Instructions Extended Double Operand (Format-I) Instructions All twelve double-operand instructions have extended versions as listed in Table 4−13. Table 4−13.Extended Double Operand Instructions Status Bits Mnemonic Operands Operation src → dst − − − − MOVX(.B,.A) src,dst src + dst → dst ADDX(.B,.A) src,dst src + dst + C →...
Page 163 MSP430X Extended Instructions The four possible addressing combinations for the extension word for format-I instructions are shown in Figure 4−29. Figure 4−29. Extended Format-I Instruction Formats n−1/Rn Op-code src.19:16 Op-code src.15:0 dst.19:16 Op-code dst.15:0 src.19:16 dst.19:16 Op-code src.15:0 dst.15:0 If the 20-bit address of a source or destination operand is located in memory, not in a CPU register, then two words are used for this operand as shown in Figure 4−30.
Page 164 MSP430X Extended Instructions Extended Single Operand (Format-II) Instructions Extended MSP430X Format-II instructions are listed in Table 4−14. Table 4−14.Extended Single-Operand Instructions Operation Status Bits Mnemonic Operands Call indirect to subroutine (20-bit address) − − − − CALLA Pop n 20-bit registers from stack 1 −...
Page 165 MSP430X Extended Instructions The three possible addressing mode combinations for format-II instructions are shown in Figure 4−31. Figure 4−31. Extended Format-II Instruction Format n−1/Rn Op-code Op-code dst.19:16 Op-code dst.15:0 Extended Format II Instruction Format Exceptions Exceptions for the Format II instruction formats are shown below. Figure 4−32.
Page 166 MSP430X Extended Instructions Figure 4−34. BRA Instruction Format Rsrc Op-code 0(PC) #imm/abs19:16 Op-code 0(PC) #imm15:0 / &abs15:0 Rsrc Op-code 0(PC) index15:0 Figure 4−35. CALLA Instruction Format Op-code Rdst Op-code Rdst index15:0 Op-code #imm/ix/abs19:16 #imm15:0 / index15:0 / &abs15:0 4-52 16-Bit MSP430X CPU...
Page 167 MSP430X Extended Instructions Extended Emulated Instructions The extended instructions together with the constant generator form the extended Emulated instructions. Table 4−15 lists the Emulated instructions. Table 4−15. xtended Emulated Instructions Instruction Explanation Emulation Add carry to dst ADCX(.B,.A) dst ADDCX(.B,.A) #0,dst Branch indirect dst BRA dst MOVA dst,PC...
Page 168 MSP430X Extended Instructions MSP430X Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the register mode and the Immediate mode, except for the MOVA instruction as listed in Table 4−16. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time.
Page 169 MSP430X Extended Instructions MSP430X Instruction Execution The number of CPU clock cycles required for an MSP430X instruction depends on the instruction format and the addressing modes used — not the instruction itself. The number of clock cycles refers to MCLK. MSP430X Format-II (Single-Operand) Instruction Cycles and Lengths Table 4−17 lists the length and the CPU cycles for all addressing modes of the MSP430X extended single-operand instructions.
Page 170 MSP430X Extended Instructions Table 4−18.MSP430X Format-I Instruction Cycles and Length No. of Length of Cycles Instruction Addressing Mode Source Destination .B/.W .B/.W/.A Examples † BITX.B R5,R8 ADDX R9,PC ‡ § X(Rm) ANDX.A R5,4(R6) ‡ § XORX R8,EDE ‡ § &EDE BITX.W R5,&EDE BITX @R5,R8 ADDX @R9,PC...
Page 171 MSP430X Extended Instructions MSP430X Address Instruction Cycles and Lengths Table 4−19 lists the length and the CPU cycles for all addressing modes of the MSP430X address instructions. Table 4−19.Address Instruction Cycles and Length Execution Length of Time MCLK Instruction Addressing Mode Cycles (Words) CMPA...
Page 172: Instruction Set Description
Instruction Set Description 4.6 Instruction Set Description The instruction map of the MSP430X shows all available instructions: 0xxx MOVA, CMPA, ADDA, SUBA, RRCM, RRAM, RLAM, RRUM 10xx RRC RRC.B SWPB RRA.B PUSH PUSH.B CALL RETI CALLA 14xx PUSHM.A, POPM.A, PUSHM.W, POPM.W 18xx Extension Word For Format I and Format II Instructions 1Cxx...
Page 173: Extended Instruction Binary Descriptions
Instruction Set Description 4.6.1 Extended Instruction Binary Descriptions Detailed MSP430X instruction binary descriptions are shown below. Instruction src or Instruction Group data.19:16 Identifier Instruction 12 11 MOVA MOVA @Rsrc,Rdst MOVA @Rsrc+,Rdst &abs.19:16 MOVA &abs20,Rdst &abs.15:0 MOVA x(Rsrc),Rdst ±15-bit index x x.15:0 &abs.19:16 MOVA Rsrc,&abs20...
Page 174 Instruction Set Description Instruction Identifier Instruction 12 11 RETI CALLA CALLA Rdst CALLA x(Rdst) x.15:0 CALLA @Rdst CALLA @Rdst+ &abs.19:16 CALLA &abs20 &abs.15:0 x.19:16 CALLA EDE x.15:0 CALLA x(PC) imm.19:16 CALLA #imm20 imm.15:0 Reserved Reserved PUSHM.A n−1 PUSHM.A #n,Rdst PUSHM.W n−1 PUSHM.W #n,Rdst POPM.A...
Page 175: Mps430 Instructions
MSP430 Instructions 4.6.2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages. 16-Bit MSP430X CPU 4-61...
Page 176 MSP430 Instructions * ADC[.W] Add carry to destination * ADC.B Add carry to destination Syntax ADC.W ADC.B Operation dst + C −> dst Emulation ADDC #0,dst ADDC.B #0,dst Description The carry bit (C) is added to the destination operand. The previous contents of the destination are lost.
Page 177 MSP430 Instructions ADD[.W] Add source word to destination word ADD.B Add source byte to destination byte Syntax src,dst or ADD.W src,dst ADD.B src,dst src + dst → dst Operation Description The source operand is added to the destination operand. The previous content of the destination is lost.
Page 178 MSP430 Instructions ADDC[.W] Add source word and carry to destination word ADDC.B Add source byte and carry to destination byte Syntax ADDC src,dst or ADDC.W src,dst ADDC.B src,dst src + dst + C → dst Operation Description The source operand and the carry bit C are added to the destination operand. The previous content of the destination is lost.
Page 179 MSP430 Instructions AND[.W] Logical AND of source word with destination word AND.B Logical AND of source byte with destination byte Syntax src,dst or AND.W src,dst AND.B src,dst src .and. dst → dst Operation Description The source operand and the destination operand are logically ANDed. The result is placed into the destination.
Page 180 MSP430 Instructions BIC[.W] Clear bits set in source word in destination word BIC.B Clear bits set in source byte in destination byte Syntax src,dst or BIC.W src,dst BIC.B src,dst (.not. src) .and. dst → dst Operation Description The inverted source operand and the destination operand are logically ANDed.
Page 181 MSP430 Instructions BIS[.W] Set bits set in source word in destination word BIS.B Set bits set in source byte in destination byte Syntax src,dst or BIS.W src,dst BIS.B src,dst src .or. dst → dst Operation Description The source operand and the destination operand are logically ORed. The result is placed into the destination.
Page 182 MSP430 Instructions BIT[.W] Test bits set in source word in destination word BIT.B Test bits set in source byte in destination byte Syntax src,dst or BIT.W src,dst BIT.B src,dst Operation src .and. dst Description The source operand and the destination operand are logically ANDed. The result affects only the status bits in SR.
Page 183 MSP430 Instructions * BR, BRANCH Branch to destination in lower 64K address space Syntax Operation dst −> PC Emulation dst,PC Description An unconditional branch is taken to an address anywhere in the lower 64K address space. All source addressing modes can be used. The branch instruction is a word instruction.
Page 184 MSP430 Instructions CALL Call a Subroutine in lower 64 K Syntax CALL dst → tmp Operation 16-bit dst is evaluated and stored SP − 2 → SP PC → @SP updated PC with return address to TOS tmp → PC saved 16-bit dst to PC Description A subroutine call is made from an address in the lower 64 K to a subroutine...
Page 185 MSP430 Instructions * CLR[.W] Clear destination * CLR.B Clear destination Syntax or CLR.W dst CLR.B Operation 0 −> dst Emulation #0,dst MOV.B #0,dst Description The destination operand is cleared. Status Bits Status bits are not affected. Example RAM word TONI is cleared. TONI ;...
Page 186 MSP430 Instructions * CLRC Clear carry bit Syntax CLRC Operation 0 −> C Emulation #1,SR Description The carry bit (C) is cleared. The clear carry instruction is a word instruction. Status Bits N: Not affected Z: Not affected C: Cleared V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected.
Page 187 MSP430 Instructions * CLRN Clear negative bit Syntax CLRN 0 → N Operation (.NOT.src .AND. dst −> dst) Emulation #4,SR Description The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction.
Page 188 MSP430 Instructions * CLRZ Clear zero bit Syntax CLRZ 0 → Z Operation (.NOT.src .AND. dst −> dst) Emulation #2,SR Description The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction.
Page 189 MSP430 Instructions CMP[.W] Compare source word and destination word CMP.B Compare source byte and destination byte Syntax src,dst or CMP.W src,dst CMP.B src,dst Operation (.not.src) + 1 + dst or dst − src Description The source operand is subtracted from the destination operand. This is made by adding the 1’s complement of the source + 1 to the destination.
Page 190 MSP430 Instructions * DADC[.W] Add carry decimally to destination * DADC.B Add carry decimally to destination Syntax DADC DADC.W src,dst DADC.B Operation dst + C −> dst (decimally) Emulation DADD #0,dst DADD.B #0,dst Description The carry bit (C) is added decimally to the destination. Status Bits N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise...
Page 191 MSP430 Instructions DADD[.W] Add source word and carry decimally to destination word DADD.B Add source byte and carry decimally to destination byte Syntax DADD src,dst or DADD.W src,dst DADD.B src,dst src + dst + C → dst (decimally) Operation Description The source operand and the destination operand are treated as two (.B) or four (.W) binary coded decimals (BCD) with positive signs.
Page 192 MSP430 Instructions * DEC[.W] Decrement destination * DEC.B Decrement destination Syntax DEC.W DEC.B Operation dst − 1 −> dst Emulation #1,dst Emulation SUB.B #1,dst Description The destination operand is decremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset.
Page 193 MSP430 Instructions * DECD[.W] Double-decrement destination * DECD.B Double-decrement destination Syntax DECD DECD.W DECD.B Operation dst − 2 −> dst Emulation #2,dst Emulation SUB.B #2,dst Description The destination operand is decremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise...
Page 194 MSP430 Instructions * DINT Disable (general) interrupts Syntax DINT 0 → GIE Operation (0FFF7h .AND. SR → SR .NOT.src .AND. dst −> dst) Emulation #8,SR Description All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR.
Page 195 MSP430 Instructions * EINT Enable (general) interrupts Syntax EINT 1 → GIE Operation (0008h .OR. SR −> SR / .src .OR. dst −> dst) Emulation #8,SR Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR.
Page 196 MSP430 Instructions * INC[.W Increment destination * INC.B Increment destination Syntax or INC.W dst INC.B Operation dst + 1 −> dst Emulation #1,dst Description The destination operand is incremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise...
Page 197 MSP430 Instructions * INCD[.W] Double-increment destination * INCD.B Double-increment destination Syntax INCD or INCD.W INCD.B Operation dst + 2 −> dst Emulation #2,dst Emulation ADD.B #2,dst Example The destination operand is incremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise...
Page 198 MSP430 Instructions * INV[.W] Invert destination * INV.B Invert destination Syntax INV.B Operation .NOT.dst −> dst Emulation #0FFFFh,dst Emulation XOR.B #0FFh,dst Description The destination operand is inverted. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT.
Page 199 MSP430 Instructions Jump if carry Jump if Higher or Same (unsigned) Syntax label label PC + (2 × Offset) → PC Operation If C = 1: If C = 0: execute the following instruction Description The carry bit C in the status register is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC.
Page 200 MSP430 Instructions JEQ,JZ Jump if equal,Jump if zero Syntax label label PC + (2 × Offset) → PC Operation If Z = 1: If Z = 0: execute following instruction Description The Zero bit Z in the status register is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC.
Page 201 MSP430 Instructions Jump if Greater or Equal (signed) Syntax label PC + (2 × Offset) → PC Operation If (N .xor. V) = 0: If (N .xor. V) = 1: execute following instruction Description The negative bit N and the overflow bit V in the status register are tested. If both bits are set or both are reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC.
Page 202 MSP430 Instructions Jump if Less (signed) Syntax label PC + (2 × Offset) → PC Operation If (N .xor. V) = 1: If (N .xor. V) = 0: execute following instruction Description The negative bit N and the overflow bit V in the status register are tested. If only one is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC.
Page 203 MSP430 Instructions Jump unconditionally Syntax label PC + (2 × Offset) → PC Operation Description The signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC. This means an unconditional jump in the range -511 to +512 words relative to the PC in the full memory.
Page 204 MSP430 Instructions Jump if Negative Syntax label PC + (2 × Offset) → PC Operation If N = 1: If N = 0: execute following instruction Description The negative bit N in the status register is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC.
Page 205 MSP430 Instructions Jump if No carry Jump if lower (unsigned) Syntax label label PC + (2 × Offset) → PC Operation If C = 0: If C = 1: execute following instruction Description The carry bit C in the status register is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC.
Page 206 MSP430 Instructions Jump if Not Zero Jump if Not Equal Syntax label label PC + (2 × Offset) → PC Operation If Z = 0: If Z = 1: execute following instruction Description The zero bit Z in the status register is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program counter PC.
Page 207 MSP430 Instructions MOV[.W] Move source word to destination word MOV.B Move source byte to destination byte Syntax src,dst or MOV.W src,dst MOV.B src,dst src → dst Operation Description The source operand is copied to the destination. The source operand is not affected.
Page 208 MSP430 Instructions * NOP No operation Syntax Operation None Emulation #0, R3 Description No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status Bits Status bits are not affected. 4-94 16-Bit MSP430X CPU...
Page 209 MSP430 Instructions * POP[.W] Pop word from stack to destination * POP.B Pop byte from stack to destination Syntax POP.B Operation @SP −> temp SP + 2 −> SP temp −> dst Emulation @SP+,dst MOV.W @SP+,dst Emulation MOV.B @SP+,dst Description The stack location pointed to by the stack pointer (TOS) is moved to the destination.
Page 210 MSP430 Instructions PUSH[.W] Save a word on the stack PUSH.B Save a byte on the stack Syntax PUSH dst or PUSH.W PUSH.B SP − 2 → SP Operation → @SP Description The 20-bit stack pointer SP is decremented by two. The operand is then copied to the RAM word addressed by the SP.
Page 211 MSP430 Instructions Return from subroutine Syntax → PC.15:0 Saved PC to PC.15:0. PC.19:16 ← 0 Operation SP + 2 → SP Description The 16-bit return address (lower 64 K), pushed onto the stack by a CALL instruction is restored to the PC. The program continues at the address following the subroutine call.
Page 212 MSP430 Instructions RETI Return from interrupt Syntax RETI → SR.15:0 Operation Restore saved status register SR with PC.19:16 SP + 2 → SP → PC.15:0 Restore saved program counter PC.15:0 SP + 2 → SP House keeping Description The status register is restored to the value at the beginning of the interrupt service routine.
Page 213 MSP430 Instructions * RLA[.W] Rotate left arithmetically * RLA.B Rotate left arithmetically Syntax RLA.W RLA.B Operation C <− MSB <− MSB−1 ..LSB+1 <− LSB <− 0 Emulation dst,dst ADD.B dst,dst Description The destination operand is shifted left one position as shown in Figure 4−38. The MSB is shifted into the carry bit (C) and the LSB is filled with 0.
Page 214 MSP430 Instructions * RLC[.W] Rotate left through carry * RLC.B Rotate left through carry Syntax RLC.W RLC.B Operation C <− MSB <− MSB−1 ..LSB+1 <− LSB <− C Emulation ADDC dst,dst Description The destination operand is shifted left one position as shown in Figure 4−39. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C).
Page 215 MSP430 Instructions RRA[.W] Rotate Right Arithmetically destination word RRA.B Rotate Right Arithmetically destination byte Syntax RRA.B dst or RRA.W dst MSB → MSB → MSB-1 . →... LSB+1 → LSB → C Operation Description The destination operand is shifted right arithmetically by one bit position as shown in Figure 4−40.
Page 216 MSP430 Instructions RRC[.W] Rotate Right through carry destination word RRC.B Rotate Right through carry destination byte Syntax dst or RRC.W dst RRC.B C → MSB → MSB-1 → ... LSB+1 → LSB → C Operation Description The destination operand is shifted right by one bit position as shown in Figure 4−41.
Page 217 MSP430 Instructions * SBC[.W] Subtract source and borrow/.NOT. carry from destination * SBC.B Subtract source and borrow/.NOT. carry from destination Syntax SBC.W SBC.B Operation dst + 0FFFFh + C −> dst dst + 0FFh + C −> dst Emulation SUBC #0,dst SUBC.B #0,dst...
Page 218 MSP430 Instructions * SETC Set carry bit Syntax SETC Operation 1 −> C Emulation #1,SR Description The carry bit (C) is set. Status Bits N: Not affected Z: Not affected C: Set V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example Emulation of the decimal subtraction: Subtract R5 from R6 decimally...
Page 219 MSP430 Instructions * SETN Set negative bit Syntax SETN Operation 1 −> N Emulation #4,SR Description The negative bit (N) is set. Status Bits N: Set Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. 16-Bit MSP430X CPU 4-105...
Page 220 MSP430 Instructions * SETZ Set zero bit Syntax SETZ Operation 1 −> Z Emulation #2,SR Description The zero bit (Z) is set. Status Bits N: Not affected Z: Set C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. 4-106 16-Bit MSP430X CPU...
Page 221 MSP430 Instructions SUB[.W] Subtract source word from destination word SUB.B Subtract source byte from destination byte Syntax src,dst or SUB.W src,dst SUB.B src,dst (.not.src) + 1 + dst → dst or dst − src → dst Operation Description The source operand is subtracted from the destination operand. This is made by adding the 1’s complement of the source + 1 to the destination.
Page 222 MSP430 Instructions SUBC[.W] Subtract source word with carry from destination word SUBC.B Subtract source byte with carry from destination byte Syntax SUBC src,dst or SUBC.W src,dst SUBC.B src,dst (.not.src) + C + dst → dst or dst − (src − 1) + C → dst Operation Description The source operand is subtracted from the destination operand.
Page 223 MSP430 Instructions SWPB Swap bytes Syntax SWPB dst.15:8 ⇔ dst.7:0 Operation Description The high and the low byte of the operand are exchanged. PC.19:16 bits are cleared in register mode. Status Bits Not affected Mode Bits OSCOFF, CPUOFF, and GIE are not affected. Example Exchange the bytes of RAM word EDE (lower 64 K).
Page 224 MSP430 Instructions Extend sign Syntax dst.7 → dst.15:8, dst.7 → dst.19:8 (Register Mode) Operation Description Register Mode: the sign of the low byte of the operand is extended into the bits Rdst.19:8 Rdst.7 = 0: Rdst.19:8 = 000h afterwards. Rdst.7 = 1: Rdst.19:8 = FFFh afterwards. Other Modes: the sign of the low byte of the operand is extended into the high byte.
Page 225 MSP430 Instructions * TST[.W] Test destination * TST.B Test destination Syntax or TST.W dst TST.B Operation dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation #0,dst CMP.B #0,dst Description The destination operand is compared with zero. The status bits are set accord- ing to the result.
Page 226 MSP430 Instructions XOR[.W] Exclusive OR source word with destination word XOR.B Exclusive OR source byte with destination byte Syntax dst or XOR.W dst XOR.B src .xor. dst → dst Operation Description The source and destination operands are exclusively ORed. The result is placed into the destination.
Page 227: Extended Instructions
Extended Instructions 4.6.3 Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space. Some MSP430X instructions require an additional word of op-code called the extension word. All addresses, indexes, and immediate numbers have 20-bit values, when preceded by the extension word. The MSP430X extended instructions are listed and described in the following pages.
Page 228 Extended Instructions * ADCX.A Add carry to destination address-word * ADCX.[W] Add carry to destination word * ADCX.B Add carry to destination byte Syntax ADCX.A ADCX ADCX.W ADCX.B Operation dst + C −> dst Emulation ADDCX.A #0,dst ADDCX #0,dst ADDCX.B #0,dst Description The carry bit (C) is added to the destination operand.
Page 229 Extended Instructions ADDX.A Add source address-word to destination address-word ADDX[.W] Add source word to destination word ADDX.B Add source byte to destination byte Syntax ADDX.A src,dst ADDX src,dst or ADDX.W src,dst ADDX.B src,dst src + dst → dst Operation Description The source operand is added to the destination operand.
Page 230 Extended Instructions ADDCX.A Add source address-word and carry to destination address-word ADDCX[.W] Add source word and carry to destination word ADDCX.B Add source byte and carry to destination byte Syntax ADDCX.A src,dst ADDCX src,dst or ADDCX.W src,dst ADDCX.B src,dst src + dst + C → dst Operation Description The source operand and the carry bit C are added to the destination operand.
Page 231 Extended Instructions ANDX.A Logical AND of source address-word with destination address-word ANDX[.W] Logical AND of source word with destination word ANDX.B Logical AND of source byte with destination byte Syntax ANDX.A src,dst ANDX src,dst or ANDX.W src,dst ANDX.B src,dst src .and. dst → dst Operation Description The source operand and the destination operand are logically ANDed.
Page 232 Extended Instructions BICX.A Clear bits set in source address-word in destination address-word BICX[.W] Clear bits set in source word in destination word BICX.B Clear bits set in source byte in destination byte Syntax BICX.A src,dst BICX src,dst or BICX.W src,dst BICX.B src,dst (.not.
Page 233 Extended Instructions BISX.A Set bits set in source address-word in destination address-word BISX[.W] Set bits set in source word in destination word BISX.B Set bits set in source byte in destination byte Syntax BISX.A src,dst BISX src,dst or BISX.W src,dst BISX.B src,dst src .or.
Page 234 Extended Instructions BITX.A Test bits set in source address-word in destination address-word BITX[.W] Test bits set in source word in destination word BITX.B Test bits set in source byte in destination byte Syntax BITX.A src,dst BITX src,dst or BITX.W src,dst BITX.B src,dst Operation...
Page 235 Extended Instructions * CLRX.A Clear destination address-word * CLRX.[W] Clear destination word * CLRX.B Clear destination byte Syntax CLRX.A CLRX or CLRX.W CLRX.B Operation 0 −> dst Emulation MOVX.A #0,dst MOVX #0,dst MOVX.B #0,dst Description The destination operand is cleared. Status Bits Status bits are not affected.
Page 236 Extended Instructions CMPX.A Compare source address-word and destination address-word CMPX[.W] Compare source word and destination word CMPX.B Compare source byte and destination byte Syntax CMPX.A src,dst CMPX src,dst or CMPX.W src,dst CMPX.B src,dst Operation (.not. src) + 1 + dst or dst − src Description The source operand is subtracted from the destination operand by adding the 1’s complement of the source + 1 to the destination.
Page 237 Extended Instructions * DADCX.A Add carry decimally to destination address-word * DADCX[.W] Add carry decimally to destination word * DADCX.B Add carry decimally to destination byte Syntax DADCX.A DADCX DADCX.W src,dst DADCX.B Operation dst + C −> dst (decimally) Emulation DADDX.A #0,dst DADDX...
Page 238 Extended Instructions DADDX.A Add source address-word and carry decimally to destination address-word DADDX[.W] Add source word and carry decimally to destination word DADDX.B Add source byte and carry decimally to destination byte Syntax DADDX.A src,dst DADDX src,dst or DADDX.W src,dst DADDX.B src,dst src + dst + C →...
Page 239 Extended Instructions * DECX.A Decrement destination address-word * DECX[.W] Decrement destination word * DECX.B Decrement destination byte Syntax DECX DECX DECX.W DECX.B Operation dst − 1 −> dst Emulation SUBX.A #1,dst SUBX #1,dst SUBX.B #1,dst Description The destination operand is decremented by one. The original contents are lost.
Page 240 Extended Instructions * DECDX.A Double-decrement destination address-word * DECDX[.W] Double-decrement destination word * DECDX.B Double-decrement destination byte Syntax DECDX.A DECDX DECDX.W DECDX.B Operation dst − 2 −> dst Emulation SUBX.A #2,dst SUBX #2,dst SUBX.B #2,dst Description The destination operand is decremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise...
Page 241 Extended Instructions * INCX.A Increment destination address-word * INCX[.W] Increment destination word * INCX.B Increment destination byte Syntax INCX.A INCX or INCX.W INCX.B Operation dst + 1 −> dst Emulation ADDX.A #1,dst ADDX #1,dst ADDX.B #1,dst Description The destination operand is incremented by one. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFFh, reset otherwise...
Page 242 Extended Instructions * INCDX.A Double-increment destination address-word * INCDX[.W] Double-increment destination word * INCDX.B Double-increment destination byte Syntax INCDX.A INCDX or INCDX.W dst INCDX.B Operation dst + 2 −> dst Emulation ADDX.A #2,dst ADDX #2,dst ADDX.B #2,dst Example The destination operand is incremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFEh, reset otherwise...
Page 243 Extended Instructions * INVX.A Invert destination * INVX[.W] Invert destination * INVX.B Invert destination Syntax INVX.A INVX or INVX.W INVX.B Operation .NOT.dst −> dst Emulation XORX.A #0FFFFFh,dst XORX #0FFFFh,dst XORX.B #0FFh,dst Description The destination operand is inverted. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFFh, reset otherwise...
Page 244 Extended Instructions MOVX.A Move source address-word to destination address-word MOVX[.W] Move source word to destination word MOVX.B Move source byte to destination byte Syntax MOVX.A src,dst MOVX src,dst or MOVX.W src,dst MOVX.B src,dst src → dst Operation Description The source operand is copied to the destination. The source operand is not affected.
Page 245 Extended Instructions Ten of the 28 possible addressing combinations of the MOVX.A instruction can use the MOVA instruction. This saves two bytes and code cycles. Examples for the addressing combinations are: MOVX.A Rsrc,Rdst MOVA Rsrc,Rdst ; Reg/Reg MOVX.A #imm20,Rdst MOVA #imm20,Rdst ;...
Page 246 Extended Instructions POPM.A Restore n CPU registers (20-bit data) from the stack POPM[.W] Restore n CPU registers (16-bit data) from the stack 1 ≤ n ≤ 16 Syntax POPM.A #n,Rdst 1 ≤ n ≤ 16 POPM.W #n,Rdst or POPM #n,Rdst Operation POPM.A: Restore the register values from stack to the specified CPU registers.
Page 247 Extended Instructions PUSHM.A Save n CPU registers (20-bit data) on the stack PUSHM[.W] Save n CPU registers (16-bit words) on the stack 1 ≤ n ≤ 16 Syntax PUSHM.A #n,Rdst 1 ≤ n ≤ 16 PUSHM.W #n,Rdst or PUSHM #n,Rdst Operation PUSHM.A: Save the 20-bit CPU register values on the stack.
Page 248 Extended Instructions * POPX.A Restore single address-word from the stack * POPX[.W] Restore single word from the stack * POPX.B Restore single byte from the stack Syntax POPX.A POPX dst or POPX.W POPX.B Operation Restore the 8/16/20-bit value from the stack to the destination. 20-bit addresses are possible.
Page 249 Extended Instructions PUSHX.A Save a single address-word on the stack PUSHX[.W] Save a single word on the stack PUSHX.B Save a single byte on the stack Syntax PUSHX.A PUSHX src or PUSHX.W PUSHX.B Operation Save the 8/16/20-bit value of the source operand on the TOS. 20-bit addresses are possible.
Page 250 Extended Instructions RLAM.A Rotate Left Arithmetically the 20-bit CPU register content RLAM[.W] Rotate Left Arithmetically the 16-bit CPU register content 1 ≤ n ≤ 4 Syntax RLAM.A #n,Rdst 1 ≤ n ≤ 4 RLAM.W #n,Rdst or RLAM #n,Rdst C ← MSB ← MSB-1 ..LSB+1 ← LSB ← 0 Operation Description The destination operand is shifted arithmetically left one, two, three, or four...
Page 251 Extended Instructions * RLAX.A Rotate left arithmetically address-word * RLAX[.W] Rotate left arithmetically word * RLAX.B Rotate left arithmetically byte Syntax RLAX.B RLAX RLAX.W RLAX.B Operation C <− MSB <− MSB−1 ..LSB+1 <− LSB <− 0 Emulation ADDX.A dst,dst ADDX dst,dst ADDX.B...
Page 252 Extended Instructions * RLCX.A Rotate left through carry address-word * RLCX[.W] Rotate left through carry word * RLCX.B Rotate left through carry byte Syntax RLCX.A RLCX RLCX.W RLCX.B Operation C <− MSB <− MSB−1 ..LSB+1 <− LSB <− C Emulation ADDCX.A dst,dst...
Page 253 Extended Instructions RRAM.A Rotate Right Arithmetically the 20-bit CPU register content RRAM[.W] Rotate Right Arithmetically the 16-bit CPU register content 1 ≤ n ≤ 4 Syntax RRAM.A #n,Rdst 1 ≤ n ≤ 4 RRAM.W #n,Rdst or RRAM #n,Rdst MSB → MSB → MSB-1 …. LSB+1 → LSB → C Operation Description The destination operand is shifted right arithmetically by one, two, three, or...
Page 254 Extended Instructions RRAX.A Rotate Right Arithmetically the 20-bit operand RRAX[.W] Rotate Right Arithmetically the 16-bit operand RRAX.B Rotate Right Arithmetically the 8-bit operand Syntax RRAX.A Rdst RRAX.W Rdst RRAX Rdst RRAX.B Rdst RRAX.A RRAX.W RRAX dst RRAX.B MSB → MSB → MSB-1 ..LSB+1 → LSB → C Operation Description Register Mode for the destination: the destination operand is shifted right by...
Page 255 Extended Instructions Example The signed 20-bit number in R5 is shifted arithmetically right four positions. RRAX.A ; R5/16 −> R5 Example The signed 8-bit value in EDE is multiplied by 0.5. RRAX.B &EDE ; EDE/2 -> EDE Figure 4−48. Rotate Right Arithmetically RRAX(.B,.A). Register Mode 0000 Figure 4−49.
Page 256 Extended Instructions RRCM.A Rotate Right through carry the 20-bit CPU register content RRCM[.W] Rotate Right through carry the 16-bit CPU register content 1 ≤ n ≤ 4 Syntax RRCM.A #n,Rdst 1 ≤ n ≤ 4 RRCM.W #n,Rdst or RRCM #n,Rdst C →...
Page 257 Extended Instructions RRCX.A Rotate Right through carry the 20-bit operand RRCX[.W] Rotate Right through carry the 16-bit operand RRCX.B Rotate Right through carry the 8-bit operand Syntax RRCX.A Rdst RRCX.W Rdst RRCX Rdst RRCX.B Rdst RRCX.A RRCX.W RRCX dst RRCX.B C →...
Page 258 Extended Instructions Example The 20-bit operand at address EDE is shifted right by one position. The MSB is loaded with 1. SETC ; Prepare carry for MSB RRCX.A ; EDE = EDE » 1 + 80000h Example The word in R6 is shifted right by twelve positions. RRCX.W ;...
Page 259 Extended Instructions RRUM.A Rotate Right Unsigned the 20-bit CPU register content RRUM[.W] Rotate Right Unsigned the 16-bit CPU register content 1 ≤ n ≤ 4 Syntax RRUM.A #n,Rdst 1 ≤ n ≤ 4 RRUM.W #n,Rdst or RRUM #n,Rdst → MSB → MSB-1 . →... LSB+1 → LSB → C Operation Description The destination operand is shifted right by one, two, three, or four bit positions...
Page 260 Extended Instructions RRUX.A Rotate Right unsigned the 20-bit operand RRUX[.W] Rotate Right unsigned the 16-bit operand RRUX.B Rotate Right unsigned the 8-bit operand Syntax RRUX.A Rdst RRUX.W Rdst RRUX Rdst RRUX.B Rdst C=0 → MSB → MSB-1 → ... LSB+1 → LSB → C Operation Description RRUX is valid for register Mode only: the destination operand is shifted right by...
Page 261 Extended Instructions * SBCX.A Subtract source and borrow/.NOT. carry from destination address-word * SBCX[.W] Subtract source and borrow/.NOT. carry from destination word * SBCX.B Subtract source and borrow/.NOT. carry from destination byte Syntax SBCX.A SBCX SBCX.W dst SBCX.B Operation dst + 0FFFFFh + C −> dst dst + 0FFFFh + C −>...
Page 262 Extended Instructions SUBX.A Subtract source address-word from destination address-word SUBX[.W] Subtract source word from destination word SUBX.B Subtract source byte from destination byte Syntax SUBX.A src,dst SUBX src,dst or SUBX.W src,dst SUBX.B src,dst (.not. src) + 1 + dst → dst or dst −...
Page 263 Extended Instructions SUBCX.A Subtract source address-word with carry from destination address-word SUBCX[.W] Subtract source word with carry from destination word SUBCX.B Subtract source byte with carry from destination byte Syntax SUBCX.A src,dst SUBCX src,dst or SUBCX.W src,dst SUBCX.B src,dst (.not. src) + C + dst → dst or dst −...
Page 264 Extended Instructions SWPBX.A Swap bytes of lower word SWPBX[.W] Swap bytes of word Syntax SWPBX.A SWPBX.W SWPBX dst.15:8 à dst.7:0 Operation Description Register Mode: Rn.15:8 are swapped with Rn.7:0. When the .A extension is used, Rn.19:16 are unchanged. When the .W extension is used, Rn.19:16 are cleared.
Page 265 Extended Instructions Figure 4−56. Swap Bytes SWPBX.A In Memory Before SWPBX.A Low Byte High Byte After SWPBX.A High Byte Low Byte Figure 4−57. Swap Bytes SWPBX[.W] Register Mode Before SWPBX High Byte Low Byte After SWPBX Low Byte High Byte Figure 4−58.
Page 266 Extended Instructions SXTX.A Extend sign of lower byte to address-word SXTX[.W] Extend sign of lower byte to word Syntax SXTX.A SXTX.W SXTX dst dst.7 → dst.15:8, Rdst.7 → Rdst.19:8 (Register Mode) Operation Description Register Mode: The sign of the low byte of the operand (Rdst.7) is extended into the bits Rdst.19:8.
Page 267 Extended Instructions Figure 4−60. Sign Extend SXTX[.W] SXTX[.W] Rdst SXTX[.W] dst 16-Bit MSP430X CPU 4-153...
Page 268 Extended Instructions * TSTX.A Test destination address-word * TSTX[.W] Test destination word * TSTX.B Test destination byte Syntax TSTX.A TSTX or TST.W dst TST.B Operation dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation CMPX.A #0,dst...
Page 269 Extended Instructions XORX.A Exclusive OR source address-word with destination address-word XORX[.W] Exclusive OR source word with destination word XORX.B Exclusive OR source byte with destination byte Syntax XORX.A src,dst XORX src,dst or XORX.W src,dst XORX.B src,dst src .xor. dst → dst Operation Description The source and destination operands are exclusively ORed.
Page 270: Address Instructions
Address Instructions 4.6.4 Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode, except for the MOVA instruction. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time.
Page 271 Address Instructions ADDA Add 20-bit source to a 20-bit destination register Syntax ADDA Rsrc,Rdst ADDA #imm20,Rdst src + Rdst → Rdst Operation Description The 20-bit source operand is added to the 20-bit destination CPU register. The previous contents of the destination are lost. The source operand is not affected.
Page 272 Address Instructions * BRA Branch to destination Syntax dst → PC Operation Emulation MOVA dst,PC Description An unconditional branch is taken to a 20-bit address anywhere in the full address space. All seven source addressing modes can be used. The branch instruction is an address-word instruction.
Page 273 Address Instructions Indirect Mode: Branch to the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect ; MOVA @R5,PC Indirect, Auto-Increment Mode: Branch to the 20-bit address contained in the words pointed to by register R5 and increment the address in R5 afterwards by 4.
Page 274 Address Instructions CALLA Call a Subroutine Syntax CALLA → tmp 20-bit dst is evaluated and stored Operation → SP SP − 2 → @SP PC.19:16 updated PC with return address to TOS (MSBs) → SP SP − 2 → @SP PC.15:0 updated PC to TOS (LSBs) →...
Page 275 Address Instructions Indirect Mode: Call a subroutine at the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indi- rect, indirect R5. CALLA ; Start address at @R5 Indirect, Auto-Increment Mode: Call a subroutine at the 20-bit address con- tained in the words pointed to by register R5 and increment the 20-bit address in R5 afterwards by 4.
Page 276 Address Instructions * CLRA Clear 20-bit destination register Syntax CLRA Rdst Operation 0 −> Rdst Emulation MOVA #0,Rdst Description The destination register is cleared. Status Bits Status bits are not affected. Example The 20-bit value in R10 is cleared. CLRA ;...
Page 277 Address Instructions CMPA Compare the 20-bit source with a 20-bit destination register Syntax CMPA Rsrc,Rdst CMPA #imm20,Rdst Operation (.not. src) + 1 + Rdst or Rdst − src Description The 20-bit source operand is subtracted from the 20-bit destination CPU register.
Page 278 Address Instructions * DECDA Double-decrement 20-bit destination register Syntax DECDA Rdst Operation Rdst − 2 −> Rdst Emulation SUBA #2,Rdst Description The destination register is decremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if Rdst contained 2, reset otherwise C: Reset if Rdst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset.
Page 279 Address Instructions * INCDA Double-increment 20-bit destination register Syntax INCDA Rdst Operation dst + 2 −> dst Emulation ADDA #2,Rdst Example The destination register is incremented by two. The original contents are lost. Status Bits N: Set if result is negative, reset if positive Z: Set if Rdst contained 0FFFFEh, reset otherwise Set if Rdst contained 0FFFEh, reset otherwise Set if Rdst contained 0FEh, reset otherwise...
Page 280 Address Instructions MOVA Move the 20-bit source to the 20-bit destination Syntax MOVA Rsrc,Rdst MOVA #imm20,Rdst MOVA z16(Rsrc),Rdst MOVA EDE,Rdst MOVA &abs20,Rdst MOVA @Rsrc,Rdst MOVA @Rsrc+,Rdst MOVA Rsrc,z16(Rdst) MOVA Rsrc,&abs20 → Rdst Operation → dst Rsrc Description The 20-bit source operand is moved to the 20-bit destination. The source operand is not affected.
Page 281 Address Instructions Copy 20-bit value R9 points to (20 bit address) to R8. R9 is incremented by four afterwards. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9+,R8 ; @R9 -> R8. R9 + 4. 2 words transferred. Copy 20-bit value in R8 to destination addressed by (R9 + 100h).
Page 282 Address Instructions * RETA Return from subroutine Syntax RETA → PC.15:0 Operation LSBs (15:0) of saved PC to PC.15:0 SP + 2 → SP → PC.19:16 MSBs (19:16) of saved PC to PC.19:16 SP + 2 → SP Emulation MOVA @SP+,PC Description The 20-bit return address information, pushed onto the stack by a CALLA...
Page 283 Address Instructions * TSTA Test 20-bit destination register Syntax TSTA Rdst Operation dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 Emulation CMPA #0,Rdst Description The destination register is compared with zero. The status bits are set according to the result.
Page 284 Address Instructions SUBA Subtract 20-bit source from 20-bit destination register Syntax SUBA Rsrc,Rdst SUBA #imm20,Rdst (.not.src) + 1 + Rdst → Rdst or Rdst − src → Rdst Operation Description The 20-bit source operand is subtracted from the 20-bit destination register. This is made by adding the 1’s complement of the source + 1 to the destination.
Page 285: Fll+ Clock Module
Chapter 5 FLL+ Clock Module The FLL+ clock module provides the clocks for MSP430x4xx devices. This chapter discusses the FLL+ clock module. The FLL+ clock module is implemented in all MSP430x4xx devices. Topic Page FLL+ Clock Module Introduction ....... FLL+ Clock Module Operation .
Page 286: Fll+ Clock Module Introduction
5.1 FLL+ Clock Module Introduction The frequency-locked loop (FLL+) clock module supports low system cost and ultra low-power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The FLL+ features digital frequency-locked loop (FLL) hardware. The FLL operates together with a digital modulator and stabilizes the internal digitally controlled oscillator (DCO) frequency to a programmable multiple of the LFXT1 watch crystal frequency.
Page 287 Figure 5−1. MSP430x43x, MSP430x44x and MSP430x461x Frequency-Locked Loop FLL_DIVx Divider /1/2/4/8 ACLK/n f Crystal ACLK OSCOFF XTS_FLL SCG0 LFOff Enable Reset XOUT XT1Off SELMx 10−bit LFXT1 Oscillator Frequency CPUOFF Integrator XCAPxPF /(N+1) − MCLK SCG1 Generator Modulator FLLDx DCOCLK DCOPLUS f DCO Divider /1/2/4/8...
Page 288 Figure 5−2. MSP430x42x and MSP430x41x Frequency-Locked Loop FLL_DIVx Divider /1/2/4/8 ACLK/n f Crystal ACLK OSCOFF XTS_FLL SCG0 LFOff Enable Reset XOUT XT1Off 10−bit LFXT1 Oscillator Frequency CPUOFF Integrator XCAPxPF /(N+1) − MCLK to CPU SCG1 Generator MCLK to Peripherals Modulator FLLDx DCOCLK DCOPLUS...
Page 289 Figure 5−3. MSP430x47x Frequency-Locked Loop FLL_DIVx Divider /1/2/4/8 ACLK/n f Crystal ACLK XTS_FLL OSCOFF SCG0 LFOff Enable Reset XOUT XT1Off SELMx 10−bit LFXT1 Oscillator Frequency CPUOFF Integrator XCAPxPF /(N+1) − MCLK SCG1 Generator Modulator FLLDx DCOCLK DCOPLUS f DCO Divider /1/2/4/8 SELS f DCO/D...
Page 290: Fll+ Clock Module Operation
FLL+ Clock Module Operation 5.2 FLL+ Clock Module Operation After a PUC, MCLK and SMCLK are sourced from DCOCLK at 32 times the ACLK frequency. When a 32,768-Hz crystal is used for ACLK, MCLK and SMCLK will stabilize to 1.048576 MHz. Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure the MSP430 operating modes and enable or disable components of the FLL+ clock module.
Page 291: Lfxt1 Oscillator
FLL+ Clock Module Operation 5.2.2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow-current consumption using a 32,768-Hz watch crystal in LF mode (XTS_FLL = 0). A watch crystal connects to XIN and XOUT without any external components. The LFXT1 oscillator supports high-speed crystals or resonators when in HF mode (XTS_FLL = 1).
Page 292: Xt2 Oscillator
FLL+ Clock Module Operation 5.2.3 XT2 Oscillator Some devices have a second crystal oscillator, XT2. XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode, except XT2 does not have internal load capacitors. The required load capacitance for the high frequency crystal or resonator must be provided externally.
Page 293: Digitally-Controlled Oscillator (Dco)
FLL+ Clock Module Operation 5.2.4 Digitally-Controlled Oscillator (DCO) The DCO is an integrated ring oscillator with RC-type characteristics. The DCO frequency is stabilized by the FLL to a multiple of ACLK as defined by N, the lowest 7 bits of the SCFQCTL register. The DCOPLUS bit sets the f frequency to f or f...
Page 294: Dco Modulator
FLL+ Clock Module Operation 5.2.6 DCO Modulator The modulator mixes two adjacent DCO frequencies to produce an intermediate effective frequency and spread the clock energy, reducing electromagnetic interference (EMI) The modulator mixes the two adjacent frequencies across 32 DCOCLK clock cycles. The error of the effective frequency is zero every 32 DCOCLK cycles and does not accumulate.
Page 295: Disabling The Fll Hardware And Modulator
FLL Operation from Low-Power Modes 5.2.7 Disabling the FLL Hardware and Modulator The FLL is disabled when the status register bit SCG0 = 1. When the FLL is disabled, the DCO runs at the previously selected tap and DCOCLK is not automatically stabilized.
Page 296: Fll+ Fail-Safe Operation
Buffered Clock Output 5.2.10 FLL+ Fail-Safe Operation The FLL+ module incorporates an oscillator-fault fail-safe feature. This feature detects an oscillator fault for LFXT1, DCO and XT2 as shown in Figure 5−5. The available fault conditions are: Low-frequency oscillator fault (LFOF) for LFXT1 in LF mode High-frequency oscillator fault (XT1OF) for LFXT1 in HF mode High-frequency oscillator fault (XT2OF) for XT2 DCO fault flag (DCOF) for the DCO...
Page 297: Fll+ Clock Module Registers
FLL+ Clock Module Registers 5.3 FLL+ Clock Module Registers The FLL+ registers are listed in Table 5−2. Table 5−2. FLL+ Registers Register Short Form Register Type Address Initial State System clock control SCFQCTL Read/write 052h 01Fh with PUC System clock frequency integrator 0 SCFI0 Read/write 050h...
Page 298 FLL+ Clock Module Registers SCFQCTL, System Clock Control Register SCFQ_M rw−0 rw−0 rw−0 rw−1 rw−1 rw−1 rw−1 rw−1 SCFQ_M Bit 7 Modulation. This enables or disables modulation Modulation enabled Modulation disabled Bits Multiplier. These bits set the multiplier value for the DCO. N must be > 0 or unpredictable operation will result.
Page 299 FLL+ Clock Module Registers SCFI1, System Clock Frequency Integrator Register 1 DCOx MODx (MSBs) rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 DCOx Bits These bits select the DCO tap and are modified automatically by the FLL+. MODx Bit 2 Most significant modulator bits.
Page 300 FLL+ Clock Module Registers FLL_CTL0, FLL+ Control Register 0 † DCOPLUS XTS_FLL XCAPxPF XT2OF XT1OF LFOF DCOF rw−0 rw−0 rw−0 rw−0 r−0 r−0 r−(1) r−1 † Not present in MSP430x41x, MSP430x42x devices DCOPLUS Bit 7 DCO output pre-divider. This bit selects if the DCO output is pre-divided before sourcing MCLK or SMCLK.
Page 301 FLL+ Clock Module Registers FLL_CTL1, FLL+ Control Register 1 SMCLK ‡ † † † LFXT1DIG XT2OFF SELMx SELS FLL_DIVx † rw−0 rw−0 rw−(1) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) † Not present in MSP430x41x, MSP430x42x devices. ‡ Only supported by MSP430xG46x and MSP430x47x devices. Otherwise unused. LFXT1DIG Bit 7 Select digital external clock source.
Page 302 FLL+ Clock Module Registers FLL_CTL2, FLL+ Control Register 2 (MSP430x47x only) XT2Sx Reserved rw−0 rw−0 XT2Sx Bits XT2 range select. These bits select the frequency range for XT2. 0.4 − 1MHz crystal or resonator 1 − 3MHz crystal or resonator 3 −...
Page 303 FLL+ Clock Module Registers IFG1, Interrupt Flag Register 1 OFIFG rw−0 Bits These bits may be used by other modules. See device-specific datasheet. OFIFG Bit 1 Oscillator fault interrupt flag. Because other bits in IFG1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 304 5-20 FLL+ Clock Module...
Page 305: Flash Memory Controller
Chapter 6 Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller. Topic Page Flash Memory Introduction ........Flash Memory Segmentation .
Page 306: Flash Memory Introduction
Flash Memory Introduction 6.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations. The controller has three or four registers (see the device-specific data sheet), a timing generator, and a voltage generator to supply program and erase voltages.
Page 307 Flash Memory Introduction Figure 6−1. Flash Memory Module Block Diagram FCTL1 Address Latch Data Latch FCTL2 Enable Address Latch FCTL3 Flash Flash Timing Memory Memory † Generator Array 2 Array 1 Enable Data Latch Programming Voltage Generator † MSP430FG461x devices only Flash Memory Controller...
Page 308: Flash Memory Segmentation
Flash Memory Segmentation 6.2 Flash Memory Segmentation MSP430FG461x devices have two flash memory arrays. Other MSP430x4xx devices have one flash array. All flash memory is partitioned into segments. Single bits, bytes, or words can be written to flash memory, but the segment is the smallest size of flash memory that can be erased.
Page 309: Segmenta On F47X Devices
Flash Memory Segmentation 6.2.1 SegmentA on F47x Devices On F47x devices SegmentA of the information memory is locked separately from all other segments with the LOCKA bit. When LOCKA = 1, SegmentA cannot be written or erased and all information memory is protected from erasure during a mass erase or production programming.
Page 310: Flash Memory Operation
Flash Memory Operation 6.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are off, and the memory operates identically to ROM. MSP430 flash memory is in-system programmable (ISP) without the need for additional external voltage.
Page 311: Erasing Flash Memory
Flash Memory Operation 6.3.2 Erasing Flash Memory The erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a segment. Erase modes are selected with the GMERAS (MSP430FG461x devices), MERAS and ERASE bits listed in Table 6−1, Table 6−2 and Table 6−3.
Page 312 Flash Memory Operation Figure 6−4. Erase Cycle Timing Erase Operation Active Remove Generate Programming Voltage Programming Voltage Erase Time, V Current Consumption is Increased BUSY or t (see device-specific data sheet) Mass Erase, Seg Erase, Global Mass Erase A dummy write to an address not in the range to be erased does not start the erase cycle, does not affect the flash memory, and is not flagged in any way.
Page 313 Flash Memory Operation Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase operation is initiated from within flash memory, all timing is controlled by the flash controller, and the CPU is held while the erase cycle completes.
Page 314 Flash Memory Operation Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not held and can continue to execute code from RAM. The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again.
Page 315: Writing Flash Memory
Flash Memory Operation 6.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed in Table 6−3. Table 6−4. Write Modes Write Mode BLKWRT Byte/word write Block write Both write modes use a sequence of individual write instructions, but using the block write mode is approximately twice as fast as byte/word mode, because the voltage generator remains on for the complete block write.
Page 316 Flash Memory Operation In byte/word mode, the internally-generated programming voltage is applied to the complete 64-byte block, each time a byte or word is written, for t WORD minus 3 f cycles. With each byte or word write, the amount of time the block is subjected to the programming voltage accumulates.
Page 317 Flash Memory Operation Initiating a Byte/Word Write from RAM The flow to initiate a byte/word write from RAM is shown in Figure 6−9. Figure 6−9. Initiating a Byte/Word Write from RAM Disable watchdog BUSY = 1 Setup flash controller and set WRT=1 Write byte or word BUSY = 1 Set WRT=0, LOCK = 1...
Page 318 Flash Memory Operation Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 64-byte block. The cumulative programming time t must not be exceeded for any block during a block write.
Page 319 Flash Memory Operation Block Write Flow and Example A block write flow is shown in Figure 6−11 and the following example. Figure 6−11. Block Write Flow Disable watchdog BUSY = 1 Setup flash controller Set BLKWRT=WRT=1 Write byte or word WAIT=0? Block Border? Set BLKWRT=0...
Page 320 Flash Memory Operation ; Write one block starting at 0F000h. ; Must be executed from RAM, Assumes Flash is already erased. 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. #32,R5 ; Use as write counter #0F000h,R6 ;...
Page 321: Flash Memory Access During Write Or Erase
Flash Memory Operation 6.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY=1, the CPU may not read or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable.
Page 322: Stopping A Write Or Erase Cycle
Flash Memory Operation 6.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller. All flash operations cease, the flash returns to read mode, and all bits in the FCTL1 register are reset.
Page 323: Flash Memory Controller Interrupts
Flash Memory Operation 6.3.8 Flash Memory Controller Interrupts The flash controller has two interrupt sources, KEYV, and ACCVIFG. ACCVIFG is set when an access violation occurs. When the ACCVIE bit is re-enabled after a flash write or erase, a set ACCVIFG flag will generate an interrupt request.
Page 324 Flash Memory Operation Figure 6−12. User-Developed Programming Solution Flash Memory Commands, data, etc. UART, Px.x, CPU executes Host MSP430 SPI, user software etc. Read/write flash memory 6-20 Flash Memory Controller...
Page 325: Flash Memory Registers
Flash Memory Registers 6.4 Flash Memory Registers The flash memory registers are listed in Table 6−6. Table 6−6. Flash Memory Registers Register Short Form Register Type Address Initial State Flash memory control register 1 FCTL1 Read/write 0128h 09600h with PUC Flash memory control register 2 FCTL2 Read/write...
Page 326 Flash Memory Registers FCTL1, Flash Memory Control Register FRKEY, Read as 096h FWKEY, Must be written as 0A5h † GMERAS ‡ BLKWRT Reserved EEIEX MERAS ERASE Reserved ‡ rw−0 rw−0 rw-0 rw−0 rw−0 † MSP430FG461x devices only. Reserved with r0 access on all other devices. ‡...
Page 327 Flash Memory Registers GMERAS Bit 3 Global mass erase, mass erase, and erase. These bits are used together to MERAS Bit 2 select the erase mode. GMERAS, MERAS and ERASE are automatically ERASE Bit 1 reset when EMEX is set or the erase operation completes. GMERAS MERAS ERASE...
Page 328 Flash Memory Registers FCTL2, Flash Memory Control Register FWKEYx, Read as 096h Must be written as 0A5h FSSELx rw−0 rw−1 rw-0 rw-0 rw-0 rw−0 rw-1 rw−0 FWKEYx Bits FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC 15-8 will be generated.
Page 329 Flash Memory Registers FCTL3, Flash Memory Control Register FCTL3 FWKEYx, Read as 096h Must be written as 0A5h † † FAIL LOCKA EMEX LOCK WAIT ACCVIFG KEYV BUSY r(w)−0 r(w)−1 rw-0 rw-1 rw−0 rw-(0) r(w)−0 † MSP430F47x devices only. Reserved with r0 access on all other devices. FWKEYx Bits FCTLx password.
Page 330 Flash Memory Registers KEYV Bit 1 Flash security key violation. This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set. KEYV must be reset with software. FCTLx password was written correctly FCTLx password was written incorrectly BUSY Bit 0...
Page 331 Flash Memory Registers FCTL4, Flash Memory Control Register FCTL4 (F47x devices only) FWKEYx, Read as 096h Must be written as 0A5h MRG1 MRG0 rw-0 rw-0 FWKEYx Bits FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC 15-8 will be generated.
Page 332 Flash Memory Registers IE1, Interrupt Enable Register 1 ACCVIE rw−0 Bits These bits may be used by other modules. See device-specific data sheet. 7-6, ACCVIE Bit 5 Flash memory access violation interrupt enable. This bit enables the ACCVIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 333: Supply Voltage Supervisor
Chapter 7 Supply Voltage Supervisor This chapter describes the operation of the SVS. The SVS is implemented in all MSP430x4xx devices. Topic Page SVS Introduction ..........SVS Operation .
Page 334: Svs Introduction
SVS Introduction 7.1 SVS Introduction The supply voltage supervisor (SVS) is used to monitor the AV supply voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user-selected threshold.
Page 335 SVS Introduction Figure 7−1. SVS Block Diagram Brownout Reset SVSIN ~ 50us 1111 0001 − SVS_POR 0010 t Reset ~ 50us 1011 SVSOUT 1100 1.2V 1101 Set SVSFG Reset PORON SVSON SVSOP SVSFG SVSCTL Bits Supply Voltage Supervisor...
Page 336: Svs Operation
SVS Operation 7.2 SVS Operation The SVS detects if the AV voltage drops below a selectable level. It can be configured to provide a POR or set a flag, when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve current consumption. 7.2.1 Configuring the SVS The VLDx bits are used to enable/disable the SVS and select one of 14...
Page 337: Changing The Vldx Bits
SVS Operation 7.2.3 Changing the VLDx Bits When the VLDx bits are changed from zero to any non-zero value, there is an automatic settling delay, t , implemented that allows the SVS circuitry d(SVSon) delay is approximately 50 μs. During this delay, the SVS to settle.
Page 338: Svs Operating Range
SVS Operation 7.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AV is close to the threshold. The SVS operation and SVS/Brownout interoperation are shown in Figure 7−2. Figure 7−2. Operating Levels for SVS and Brownout/Reset Circuit Software Sets VLD>0 V hys(SVS_IT−) V (SVS_IT−)
Page 339: Svs Registers
SVS Registers 7.3 SVS Registers The SVS registers are listed in Table 7−1. Table 7−1. SVS Registers Register Short Form Register Type Address Initial State SVS Control Register SVSCTL Read/write 056h Reset with BOR SVSCTL, SVS Control Register VLDx PORON SVSON SVSOP SVSFG...
Page 340 Supply Voltage Supervisor...
Page 341: Bit Hardware Multiplier
Chapter 8 16-Bit Hardware Multiplier This chapter describes the 16-bit hardware multiplier. The hardware multiplier is implemented in MSP430x44x devices. Topic Page Hardware Multiplier Introduction ....... Hardware Multiplier Operation .
Page 342: Hardware Multiplierintroduction
Hardware MultiplierIntroduction 8.1 Hardware MultiplierIntroduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions.
Page 343: Hardware Multiplier Operation
Hardware Multiplier Operation 8.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and signed multiply accumulate operations. The type of operation is selected by the address the first operand is written to. The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers, RESLO, RESHI, and SUMEXT.
Page 344: Result Registers
Hardware Multiplier Operation 8.2.2 Result Registers The result low register RESLO holds the lower 16-bits of the calculation result. The result high register RESHI contents depend on the multiply operation and are listed in Table 8−2. Table 8−2. RESHI Contents Mode RESHI Contents Upper 16-bits of the result...
Page 345: Software Examples
Hardware Multiplier Operation 8.2.3 Software Examples Examples for all multiplier modes follow. All 8x8 modes use the absolute address for the registers because the assembler will not allow .B access to word registers when using the labels from the standard definitions file. ;...
Page 346: Indirect Addressing Of Reslo
Hardware Multiplier Operation 8.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers, At least one instruction is needed between loading the second operand and accessing one of the result registers: ; Access multiplier results with indirect addressing #RESLO,R5 ;...
Page 347: Hardware Multiplier Registers
Hardware Multiplier Registers 8.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 8−4. Table 8−4. Hardware Multiplier Registers Register Short Form Register Type Address Initial State Operand one - multiply Read/write 0130h Unchanged Operand one - signed multiply MPYS Read/write 0132h...
Page 348 16-Bit Hardware Multiplier...
Page 349: Bit Hardware Multiplier
Chapter 9 32-Bit Hardware Multiplier This chapter describes the 32-bit hardware multiplier (MPY32). The 32-bit hardware multiplier is implemented in the MSP430x47x devices. Topic Page 32-Bit Hardware Multiplier Introduction ......32-Bit Hardware Multiplier Operation .
Page 350: Bit Hardware Multiplier Introduction
32-Bit Hardware Multiplier Introduction 9.1 32-Bit Hardware Multiplier Introduction The 32-bit hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions.
Page 351 32-Bit Hardware Multiplier Introduction Figure 9−1. 32-Bit Hardware Multiplier Block Diagram Accessible Register MPYS MACS MPY32H MPY32L MPYS32H MPYS32L MAC32H MAC32L MACS32H MACS32L OP2H OP2L OP1 (high word) OP1 (low word) OP2 (high word) OP2 (low word) 16− bit Multiplexer 16−...
Page 352: Bit Hardware Multiplier Operation
32-Bit Hardware Multiplier Operation 9.2 32-Bit Hardware Multiplier Operation The hardware multiplier supports 8-bit, 16-bit, 24-bit and 32-bit operands with unsigned multiply, signed multiply, unsigned multiply accumulate, and signed multiply accumulate operations. The size of the operands are defined by the address the operand is written to and if it is written as word or byte.
Page 353: Operand Registers
32-Bit Hardware Multiplier Operation 9.2.1 Operand Registers Operand one OP1 has twelve registers, shown in Table 9−2, used to load data into the multiplier and also select the multiply mode. Writing the low-word of the first operand to a given address selects the type of multiply operation to be performed but does not start any operation.
Page 354 32-Bit Hardware Multiplier Operation Table 9−3. OP2 registers OP2 Register Name Operation Start multiplication with 16-bit wide operand two OP2 (operand bits 0 up to 15) OP2L Start multiplication with 32-bit wide operand two OP2 (operand bits 0 up to 15) OP2H Continue multiplication with 32-bit wide operand two OP2 (operand bits 16 up to 31)
Page 355: Result Registers
32-Bit Hardware Multiplier Operation 9.2.2 Result Registers The multiplication result is always 64-bits wide. It is accessible via registers RES0 to RES3. Used with a signed operation MPYS or MACS the results are appropriately sign extended. If the result registers are loaded with initial values before a MACS operation the user software must take care that the written value is properly sign extended to 64 bits.
Page 356 32-Bit Hardware Multiplier Operation MACS Underflow and Overflow The multiplier does not automatically detect underflow or overflow in MACS mode. For example working with 16-bit input data and 32-bit results, i.e. using just RESLO and RESHI, the available range for positive numbers is 0 to 07FFF FFFFh and for negative numbers is 0FFFF FFFFh to 08000 0000h.
Page 357: Software Examples
32-Bit Hardware Multiplier Operation 9.2.3 Software Examples Examples for all multiplier modes follow. All 8×8 modes use the absolute address for the registers because the assembler will not allow .B access to word registers when using the labels from the standard definitions file. There is no sign extension necessary in software.
Page 358: Fractional Numbers
32-Bit Hardware Multiplier Operation 9.2.4 Fractional Numbers The 32-bit multiplier provides support for fixed-point signal processing. In fixed−point signal processing, fractional number are represented by using a fixed decimal point. To classify different ranges of decimal numbers, a Q-format is used. Different Q-formats represent different locations of the decimal point.
Page 359 32-Bit Hardware Multiplier Operation Fractional Number Mode Multiplying two fractional numbers using the default multiplication mode with MPYFRAC = 0 and MPYSAT = 0 gives a result with 2 sign bits. For example if two 16-bit Q15 numbers are multiplied a 32-bit result in Q30 format is obtained.
Page 360 32-Bit Hardware Multiplier Operation Saturation Mode The multiplier prevents overflow and underflow of signed operations in saturation mode. The saturation mode is enabled with MPYSAT = 1 in register MPY32CTL0. If an overflow occurs the result is set to the most positive value available.
Page 361 32-Bit Hardware Multiplier Operation Figure 9−4 shows the flow for 32-bit saturation used for 16×16 bit multiplications and the flow for 64-bit saturation used in all other cases. Primarily, the saturated results depends on the carry bit MPYC and the most significant bit of the result.
Page 362 32-Bit Hardware Multiplier Operation The following example illustrates a special case showing the saturation function in fractional mode. It also uses the 8-bit functionality of the MPY32 module. ; Turn on fractional and saturation mode, ; clear all other bits in MPY32CTL0: #MPYSAT+MPYFRAC,&MPY32CTL0 ;Pre−load result registers to demonstrate overflow #0,&RES3...
Page 363: Putting It All Together
32-Bit Hardware Multiplier Operation 9.2.5 Putting it all together Figure 9−5 shows the complete multiplication flow depending on the various selectable modes for the MPY32 module. Figure 9−5. Multiplication Flow Chart New Multiplication started 16x16 MAC or MACS MAC or MACS MPYSAT=1 MPYSAT=1 Clear Result:...
Page 364 32-Bit Hardware Multiplier Operation Given the separation in processing of 16-bit operations (32-bit results) and 32-bit operations (64-bit results) by the module, it is important to understand the implications when using MAC/MACS operations and mixing 16-bit operands/results with 32-bit operands/results. User software must address these points during usage when mixing these operations.
Page 365: Indirect Addressing Of Result Registers
32-Bit Hardware Multiplier Operation Even though the result registers were loaded with all zeros the final result is saturated. This is because the MPYC bit was set causing the result used for the multiply-and-accumulate to be saturated to 08000 0000h. Adding a negative number to it would again cause an underflow thus the final result is also saturated to 08000 0000h.
Page 366: Using Interrupts
32-Bit Hardware Multiplier Operation 9.2.7 Using Interrupts If an interrupt occurs after writing OP1, but before writing OP2, and the multiplier is used in servicing that interrupt, the original multiplier mode selection is lost and the results are unpredictable. To avoid this, disable interrupts before using the hardware multiplier, do not use the multiplier in interrupt service routines, or use the save and restore functionality of the 32-bit multiplier.
Page 367 32-Bit Hardware Multiplier Operation Save and Restore If the multiplier is used in interrupt service routines its state can be saved and restored using the MPY32CTL0 register. The following code example shows how the complete multiplier status can be saved and restored to allow inter- ruptible multiplications together with the usage of the multiplier in interrupt ser- vice routines.
Page 368: Using Dma
32-Bit Hardware Multiplier Operation 9.2.8 Using DMA In devices with a DMA controller the multiplier can trigger a transfer when the complete result is available. The DMA controller needs to start reading the re- sult with MPY32RES0 successively up to MPY32RES3. Not all registers need to be read.
Page 369: Bit Hardware Multiplier Registers
32-Bit Hardware Multiplier Registers 9.3 32-Bit Hardware Multiplier Registers The 32-bit hardware multiplier registers are listed in Table 9−7. Table 9−7. 32-bit Hardware Multiplier Registers Register Short Form Register Address Initial State Type 16-bit operand one − multiply Read/write 0130h Unchanged 8-bit operand one −...
Page 370 32-Bit Hardware Multiplier Registers The registers listed in Table 9−8 are treated equally. Table 9−8. Alternative Registers Register Alternative 1 Alternative 2 16-bit operand one − multiply MPY32L 8-bit operand one − multiply MPY_B MPYS32L_B 16-bit operand one − signed multiply MPYS MPYS32L 8-bit operand one −...
Page 371 32-Bit Hardware Multiplier Registers MPY32CTL0, 32-bit Multiplier Control Register 0 Reserved r−0 r−0 r−0 r−0 r−0 r−0 r−0 r−0 MPYMx MPYSAT MPYFRAC Reserved MPYC OP2_32 OP1_32 rw−0 rw−0 rw−0 Reserved Bits Reserved 15−8 Bit 7 Multiplier bit-width of operand 2 OP2_32 16 bits 32 bits...
Page 372 9-24 32-Bit Hardware Multiplier...
Page 373: Dma Controller
Chapter 10 DMA Controller The DMA controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller. One DMA channel is implemented in MSP430FG43x and three DMA channels are implemented in MSP430FG461x devices. Topic Page 10.1 DMA Introduction...
Page 374: Dma Introduction
DMA Introduction 10.1 DMA Introduction The direct memory access (DMA) controller transfers data from one address to another, without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC12 conversion memory to RAM. Devices that contain a DMA controller may have one, two, or three DMA channels available.
Page 375 DMA Introduction Figure 10−1. DMA Controller Block Diagram DMA0TSELx JTAG Active NMI Interrupt Request Halt DMAREQ 0000 ENNMI TACCR2_CCIFG 0001 ROUNDROBIN TBCCR2_CCIFG 0010 Serial data received 0011 DMADSTINCRx DMADTx Serial transmit ready 0100 DMADSTBYTE DAC12_0IFG 0101 0110 ADC12IFGx DMA Channel 0 0111 TACCR0_CCIFG TBCCR0_CCIFG...
Page 376: Dma Operation
DMA Operation 10.2 DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 10.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable.
Page 377: Dma Transfer Modes
DMA Operation 10.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 10−1. Each channel is individually configurable for its transfer mode. For example, channel 0 may be configured in single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates in repeated block mode.
Page 378 DMA Operation Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state diagram is shown in Figure 10−3. The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer.
Page 379 DMA Operation Figure 10−3. DMA Single Transfer State Diagram DMAEN = 0 Reset DMAEN = 0 DMAEN = 0 DMAEN = 1 DMAREQ = 0 T_Size → DMAxSZ DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd [ DMADTx = 0 AND DMAxSZ = 0] OR DMAEN = 0 DMAABORT = 1...
Page 380 DMA Operation Block Transfers In block transfer mode, a transfer of a complete block of data occurs after one trigger. When DMADTx = 1, the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered.
Page 381 DMA Operation Figure 10−4. DMA Block Transfer State Diagram DMAEN = 0 Reset DMAEN = 0 DMAEN = 0 DMAREQ = 0 DMAEN = 1 T_Size → DMAxSZ DMAxSZ → T_Size [DMADTx = 1 DMAxSA → T_SourceAdd AND DMAxSZ = 0] DMAxDA →...
Page 382 DMA Operation Burst-Block Transfers In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes 2 MCLK cycles after every four byte/word transfers of the block resulting in 20% CPU execution capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared.
Page 383 DMA Operation Figure 10−5. DMA Burst-Block Transfer State Diagram DMAEN = 0 Reset DMAEN = 0 DMAEN = 0 DMAREQ = 0 DMAEN = 1 T_Size → DMAxSZ DMAxSZ → T_Size [DMADTx = {2, 3} DMAxSA → T_SourceAdd DMAxDA → T_DestAdd AND DMAxSZ = 0] DMAEN = 0 DMAABORT = 1...
Page 384: Initiating Dma Transfers
DMA Operation 10.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in Table 10−2.The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur.
Page 385 DMA Operation Table 10−2. DMA Trigger Operation DMAxTSELx Operation 0000 A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer starts 0001 A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag is automatically reset when the transfer starts.
Page 386: Stopping Dma Transfers
DMA Operation 10.2.4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress: A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in register DMACTL1. A burst-block transfer may be stopped by clearing the DMAEN bit. 10.2.5 DMA Channel Priorities The default DMA channel priorities are DMA0−DMA1−DMA2.
Page 387: Dma Transfer Cycle Time
DMA Operation 10.2.6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after synchronization, and one cycle of wait time after the transfer.
Page 388: Using Dma With System Interrupts
DMA Operation 10.2.7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the completion of the transfer. NMI interrupts can interrupt the DMA controller if the ENNMI bit is set. System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine or other routine must execute with no interruptions, the DMA controller should be disabled prior to executing the routine.
Page 389 DMA Operation DMAIV Software Example The following software example shows the recommended use of DMAIV and the handling overhead. The DMAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 390: Using Adc12 With The Dma Controller
DMA Operation 10.2.9 Using the USCI_B I C Module with the DMA Controller The USCI_B I C module provides two trigger sources for the DMA controller. The USCI_B I C module can trigger a transfer when new I C data is received and when data is needed for transmit.
Page 391: Dma Registers
DMA Registers 10.3 DMA Registers The DMA registers for MSP430FG43x devices are listed in Table 10−4. The DMA registers for MSP430FG461x devices are listed in Table 10−5. Table 10−4. DMA Registers, MSP430FG43x devices Register Short Form Register Type Address Initial State DMA control 0 DMACTL0 Read/write...
Page 392 DMA Registers DMACTL0, DMA Control Register 0 Reserved DMA2TSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) DMA1TSELx DMA0TSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Reserved Bits Reserved 15−12 DMA2 Bits DMA trigger select. These bits select the DMA transfer trigger. TSELx 11−8 0000 DMAREQ bit (software trigger)
Page 393 DMA Registers DMACTL1, DMA Control Register 1 ROUND ENNMI ONFETCH ROBIN rw−(0) rw−(0) rw−(0) Reserved Bits Reserved. Read only. Always read as 0. 15−3 Bit 2 DMA on fetch ONFETCH The DMA transfer occurs immediately The DMA transfer occurs on next instruction fetch after the trigger ROUND Bit 1 Round robin.
Page 394 DMA Registers DMAxCTL, DMA Channel x Control Register Reserved DMADTx DMADSTINCRx DMASRCINCRx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) DMALEVEL DMAEN DMAIFG DMAIE DMAREQ DSTBYTE SRCBYTE ABORT rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Reserved Bit 15 Reserved DMADTx Bits DMA Transfer mode.
Page 395 DMA Registers Bit 6 DMA source byte. This bit selects the source as a byte or word. SRCBYTE Word Byte Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive LEVEL triggers. Edge sensitive (rising edge) Level sensitive (high level) DMAEN Bit 4 DMA enable...
Page 396 DMA Registers DMAxSA, DMA Source Address Register Reserved Reserved DMAxSAx DMAxSAx DMAxSAx Reserved Bits Reserved 31−20 DMAxSAx Bits DMA source address. The source address register points to the DMA source 19−0 address for single transfers or the first source address for block transfers. The source address register remains unchanged during block and burst-block transfers.
Page 397 DMA Registers DMAxDA, DMA Destination Address Register Reserved Reserved DMAxDAx DMAxDAx DMAxDAx Reserved Bits Reserved 31−20 DMAxDAx Bits DMA destination address. The destination address register points to the 19−0 destination address for single transfers or the first address for block transfers. The DMAxDA register remains unchanged during block and burst-block transfers.
Page 398 DMA Registers DMAxSZ, DMA Size Address Register DMAxSZx DMAxSZx DMAxSZx Bits DMA size. The DMA size register defines the number of byte/word data per 15−0 block transfer. DMAxSZ register decrements with each word or byte transfer. When DMAxSZ decrements to 0, it is immediately and automatically reloaded with its previously initialized value.
Page 399 DMA Registers DMAIV, DMA Interrupt Vector Register DMAIVx r−(0) r−(0) r−(0) Bits DMA Interrupt Vector value DMAIVx 15-0 Interrupt Priority DMAIV Contents Interrupt Source Interrupt Flag No interrupt pending − DMA channel 0 DMA0IFG Highest DMA channel 1 DMA1IFG DMA channel 2 DMA2IFG Reserved −...
Page 400 10-28 DMA Controller...
Page 401: Digital I/O
Chapter 11 Digital I/O This chapter describes the operation of the digital I/O ports. Topic Page 11.1 Digital I/O Introduction ........11-2 11.2 Digital I/O Operation .
Page 402: Digital I/O Introduction
Digital I/O Introduction 11.1 Digital I/O Introduction MSP430 devices have up to 10 digital I/O ports implemented, P1 to P10. Each port has eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read or written to. Ports P1 and P2 have interrupt capability.
Page 403: Digital I/O Operation
Digital I/O Operation 11.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of the digital I/O is discussed in the following sections. Each port register is an 8-bit register and is accessed with byte instructions. Registers for P7−P8 and P9−P10 are arranged such that the two ports can be addressed at once as a 16-bit port.
Page 404: Pullup/Pulldown Resistor Enable Registers Pxren (Msp430X47X Only)
Digital I/O Operation 11.2.4 Pullup/Pulldown Resistor Enable Registers PxREN (MSP430x47x only) In MSP430x47x devices all port pins have a programmable pull-up/down resistor. Each bit in each PxREN register enables or disables the pull-up/down resistor of the corresponding I/O pin. The corresponding bit in the PxOUT register selects if the pin is pulled up or pulled down.
Page 405: P1 And P2 Interrupts
Digital I/O Operation 11.2.6 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector, and all P2 pins source a different single interrupt vector. The PxIFG register can be tested to determine the source of a P1 or P2 interrupt.
Page 406: Configuring Unused Port Pins
Digital I/O Operation Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin. Bit = 0: The PxIFGx flag is set with a low-to-high transition Bit = 1: The PxIFGx flag is set with a high-to-low transition Note: Writing to PxIESx Writing to P1IES, or P2IES can result in setting the corresponding interrupt flags.
Page 407: Digital I/O Registers
Digital I/O Registers 11.3 Digital I/O Registers The digital I/O registers are listed in Table 11−1 and Table 11−2. Table 11−1. Digital I/O Registers, P1-P6 Port Register Short Form Address Register Type Initial State P1IN 020h Read only − Input P1OUT 021h Read/write...
Page 408 Digital I/O Registers Table 11−2. Digital I/O Registers, P7-P10 Port Register Short Form Address Register Type Initial State P7IN 038h Read only − Input P7OUT 03Ah Read/write Unchanged Output Direction P7DIR 03Ch Read/write Reset with PUC Port Select P7SEL 03Eh Read/write Reset with PUC Resistor Enable...
Page 409: Watchdog Timer, Watchdog Timer+
Chapter 12 Watchdog Timer, Watchdog Timer+ The watchdog timer is a 16-bit timer that can be used as a watchdog or as an interval timer. This chapter describes the watchdog timer. The watchdog timer is implemented in all MSP430x4xx devices, except those with the enhanced watchdog timer, WDT+.
Page 410: Watchdog Timer Introduction
Watchdog Timer Introduction 12.1 Watchdog Timer Introduction The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
Page 411 Watchdog Timer Introduction Figure 12−1. Watchdog Timer Block Diagram WDTCTL WDTQn Int. Flag 16−bit Password Pulse Counter Compare Generator 16−bit Clear (Asyn) Write Enable Low Byte Fail-Safe R / W † MCLK † Logic SMCLK WDTHOLD ACLK WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTIS1...
Page 412: Watchdog Timer Operation
Watchdog Timer Operation 12.2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer with the WDTCTL register. The WDTCTL register also contains control bits to configure the RST/NMI pin. WDTCTL is a 16-bit, password-protected, read/write register.
Page 413: Watchdog Timer Interrupts
Watchdog Timer Operation Note: Modifying the Watchdog Timer The WDT interval should be changed together with WDTCNTCL = 1 in a single instruction to avoid an unexpected immediate PUC or interrupt. The WDT should be halted before changing the clock source to avoid a possible incorrect interval.
Page 414: Operation In Low-Power Modes
Watchdog Timer Operation 12.2.6 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signals are available in different low-power modes. The requirements of the user’s application and the type of clocking used determine how the WDT should be configured.
Page 415: Watchdog Timer Registers
Watchdog Timer Registers 12.3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 12−1. Table 12−1.Watchdog Timer Registers Register Short Form Register Type Address Initial State Watchdog timer control register WDTCTL Read/write 0120h 06900h with PUC SFR interrupt enable register 1 Read/write 0000h Reset with PUC...
Page 416 Watchdog Timer Registers WDTCTL, Watchdog Timer Register Read as 069h WDTPW, must be written as 05Ah WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx rw−0 rw−0 rw−0 rw−0 r0(w) rw−0 rw−0 rw−0 WDTPW Bits Watchdog timer password. Always read as 069h. Must be written as 05Ah, or 15-8 a PUC will be generated.
Page 417 Watchdog Timer Registers IE1, Interrupt Enable Register 1 NMIIE WDTIE rw−0 rw−0 Bits These bits may be used by other modules. See device-specific datasheet. NMIIE Bit 4 NMI interrupt enable. This bit enables the NMI interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 418 Watchdog Timer Registers IFG1, Interrupt Flag Register 1 NMIIFG WDTIFG rw−(0) rw−(0) Bits These bits may be used by other modules. See device-specific datasheet. NMIIFG Bit 4 NMI interrupt flag. NMIIFG must be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear NMIIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 419: Basic Timer1
Chapter 13 Basic Timer1 The Basic Timer1 module is two independent, cascadable 8-bit timers. This chapter describes the Basic Timer1. Basic Timer1 is implemented in all MSP430x4xx devices. Topic Page 13.1 Basic Timer1 Introduction ........13-2 13.2 Basic Timer1 Operation .
Page 420: Basic Timer1 Introduction
Basic Timer1 Introduction 13.1 Basic Timer1 Introduction The Basic Timer1 supplies LCD timing and low frequency time intervals. The Basic Timer1 is two independent 8-bit timers that can also be cascaded to form one 16-bit timer function. Some uses for the Basic Timer1 include: Real-time clock (RTC) function Software time increments Basic Timer1 features include:...
Page 421 Basic Timer1 Introduction Figure 13−1. Basic Timer1 Block Diagram BTDIV BTHOLD BTCNT1 BTFRFQx ACLK CLK1 Q4 Q5 Q6 Q7 f LCD BTSSEL ACLK:256 BTCNT2 BTIPx CLK2 SMCLK Q4 Q5 Q6 Q7 Set_BTIFG Basic Timer1 13-3...
Page 422: Basic Timer1 Operation
Basic Timer1 Introduction 13.2 Basic Timer1 Operation The Basic Timer1 module can be configured as two 8-bit timers or one 16-bit timer with the BTCTL register. The BTCTL register is an 8-bit, read/write register. Any read or write access must use byte instructions. The Basic Timer1 controls the LCD frame frequency with BTCNT1.
Page 423: Basic Timer1 Interrupts
Basic Timer1 Introduction 13.2.4 Basic Timer1 Operation: Signal f The LCD controller (but not the LCD_A controller) uses the f signal from the BTCNT1 to generate the timing for common and segment lines. ACLK sources BTCNT1 and is assumed to be 32768 Hz for generating f .
Page 424: Basic Timer1 Registers
Basic Timer1 Introduction 13.3 Basic Timer1 Registers The watchdog timer module registers are listed in Table 13−1. Table 13−1.Basic Timer1 Registers Register Short Form Register Type Address Initial State Basic Timer1 Control BTCTL Read/write 040h Unchanged Basic Timer1 Counter 1 BTCNT1 Read/write 046h...
Page 425 Basic Timer1 Introduction BTCTL, Basic Timer1 Control Register BTSSEL BTHOLD BTDIV BTFRFQx BTIPx BTSSEL Bit 7 BTCNT2 clock select. This bit, together with the BTDIV bit, selects the clock source for BTCNT2. See the description for BTDIV. BTHOLD Bit 6 Basic Timer1 Hold.
Page 426 Basic Timer1 Introduction BTCNT1, Basic Timer1 Counter 1 BTCNT1x BTCNT1x Bits BTCNT1 register. The BTCNT1 register is the count of BTCNT1. 7−0 BTCNT2, Basic Timer1 Counter 2 BTCNT2x BTCNT2x Bits BTCNT2 register. The BTCNT2 register is the count of BTCNT2. 7−0 13-8 Basic Timer1...
Page 427 Basic Timer1 Introduction IE2, Interrupt Enable Register 2 BTIE rw−0 BTIE Bit 7 Basic Timer1 interrupt enable. This bit enables the BTIFG interrupt. Because other bits in IE2 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 428 13-10 Basic Timer1...
Page 429: Real Time Clock
Chapter 14 Real Time Clock The Real-Time Clock module is a 32-bit counter module with calendar function. This chapter describes the Real-Time Clock (RTC) module. The RTC is implemented in MSP430FG461x devices. Topic Page 14.1 Real-Time Clock Introduction ....... . . 14-2 14.2 Real-Time Clock Operation .
Page 430: Rtc Introduction
RTC Introduction 14.1 RTC Introduction The Real-Time Clock (RTC) module can be used as a general-purpose 32-bit timer or as a RTC with calendar function. RTC features include: Calender and clock mode 32-bit counter mode with selectable clock sources Automatic counting of seconds, minutes, hours, day of week, day of month, month and year in calender mode.
Page 431 RTC Introduction Figure 14−1. Real-Time Clock ACLK Basic Timer BTCNT2.Q6 SMCLK RTCMODEx RTCHOLD RTCBCD Mode RTCNT4/ RTCNT3/ RTCNT2/ RTCNT1/ RTCDOW RTCHOUR RTCMIN RTCSEC RTCTEVx 8−bit overflow / minute changed 16−bit overflow / hour changed Set_RTCFG 24−bit overflow / RTCHOUR = Midnight RTCIE 32−bit overflow / RTCHOUR = Noon Set_BTIFG...
Page 432: Real-Time Clock Operation
Real-Time Clock Operation 14.2 Real-Time Clock Operation The Real-Time Clock module can be configured as a real-time clock with calendar function or as a 32-bit general-purpose counter with the RTCMODEx bits. 14.2.1 Counter Mode Counter mode is selected when RTCMODEx < 11. In this mode, a 32-bit counter is provided that is directly accessible by software.
Page 433: Calendar Mode
Real-Time Clock Operation 14.2.2 Calendar Mode Calendar mode is selected when RTCMODEx = 11. In calendar mode the RTC provides seconds, minutes, hours, day of week, day of month, month, and year in selectable BCD or hexadecimal format. Switching from counter to calendar mode clears the seconds, minutes, hours, day-of-week, and year counts and sets day-of-month and month counts to 1.
Page 434: Real-Time Clock Interrupts
Real-Time Clock Operation 14.2.4 Real-Time Clock Interrupts The Real-Time Clock uses two bits for interrupt control. Basic Timer1 interrupt flag, BTIFG, located in IFG2.7 Real-Time Clock interrupt enable, RTCIE, located in the module The Real-Time Clock module shares the Basic Timer1 interrupt flag and vector.
Page 435: Real-Time Clock Registers
Real-Time Clock Registers 14.3 Real-Time Clock Registers The Real-Time Clock registers are listed in Table 14−2 for byte access. They may be accessed with word instructions as listed in Table 14−3. Table 14−2.Real-Time Clock Registers Register Short Form Register Type Address Initial State Real-Time Clock control register RTCCTL...
Page 436 Real-Time Clock Registers RTCCTL, Real-Time Clock Control Register RTCBCD RTCHOLD RTCMODEx RTCTEVx RTCIE RTCFG rw-(0) rw-(1) rw-(0) rw-(0) rw-(0) rw-(0) rw-0 rw-0 RTCBCD Bit 7 BCD format select. This bit selects BCD format for the calendar registers when RTCMODEx = 11. Hexadecimal format BCD format RTCHOLD...
Page 437 Real-Time Clock Registers RTCNT1, RTC Counter 1, Counter Mode RTCNT1x RTCNT1x Bits RTCNT1 register. The RTCNT1 register is the count of RTCNT1. 7−0 RTCNT2, RTC Counter 2, Counter Mode RTCNT2x RTCNT2x Bits RTCNT2 register. The RTCNT2 register is the count of RTCNT2. 7−0 RTCNT3, RTC Counter 3, Counter Mode RTCNT3x...
Page 438 Real-Time Clock Registers RTCSEC, RTC Seconds Register, Calendar Mode with Hexadecimal Format Seconds (0...59) RTCSEC, RTC Seconds Register, Calendar Mode with BCD Format Seconds - high digit (0...5) Seconds - low digit (0...9) RTCMIN, RTC Minutes Register, Calendar Mode with Hexadecimal Format Minutes (0...59) RTCMIN, RTC Minutes Register, Calendar Mode with BCD Format Minutes - high digit (0...5)
Page 439 Real-Time Clock Registers RTCHOUR, RTC Hours Register, Calendar Mode with Hexadecimal Format Hours (0...24) RTCHOUR, RTC Hours Register, Calendar Mode with BCD Format Hours high digit (0...2) Hours low digit (0...9) RTCDOW, RTC Day-of-Week Register, Calendar Mode Day-of-Week (0...6) Real Time Clock 14-11...
Page 440 Real-Time Clock Registers RTCDAY, RTC Day-of-Month Register, Calendar Mode with Hexadecimal Format Day-of-Month (1...28,29,30,31) RTCDAY, RTC Day-of-Month Register, Calendar Mode with BCD Format Day-of-Month high digit Day-of-Month low digit (0...9) (0...3) RTCMON, RTC Month Register, Calendar Mode with Hexadecimal Format Month (1..12) RTCMON, RTC Month Register, Calendar Mode with BCD Format Month high...
Page 441 Real-Time Clock Registers RTCYEARL, RTC Year Low-Byte Register, Calendar Mode with Hexadecimal Format Year Low Byte of 0...4095 RTCYEARL, RTC Year Low-Byte Register, Calendar Mode with BCD Format Decade (0...9) Year lowest digit (0...9) RTCYEARH, RTC Year High-Byte Register, Calendar Mode with Hexadecimal Format Year High Byte of 0...4095 RTCYEARH, RTC Year High-Byte Register, Calendar Mode with BCD Format Century high digit (0...4)
Page 442 Real-Time Clock Registers IE2, Interrupt Enable Register 2 BTIE rw-0 BTIE Bit 7 Basic Timer1 interrupt enable. This bit enables the BTIFG interrupt. Because other bits in IE2 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions.
Page 443: Timer_A
Chapter 15 Timer_A Timer_A is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes Timer_A. This chapter describes the operation of the Timer_A of the MSP430x4xx device family. Topic Page 15.1 Timer_A Introduction ......... 15-2 15.2 Timer_A Operation .
Page 444: Timer_A Introduction
Timer_A Introduction 15.1 Timer_A Introduction Timer_A is a 16-bit timer/counter with three or five capture/compare registers. Timer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Page 445 Timer_A Introduction Figure 15−1. Timer_A Block Diagram Timer Block Timer Clock TASSELx 16−bit Timer TACLK Divider Count EQU0 1/2/4/8 Mode ACLK Clear SMCLK Set TAIFG TACLR CCR0 CCR1 CCR2 CCR3 CCR4 CCISx logic CCI4A Capture Mode CCI4B TACCR4 Timer Clock Sync Compararator 4 EQU4...
Page 446: Timer_A Operation
Timer_A Operation 15.2 Timer_A Operation The Timer_A module is configured with user software. The setup and operation of Timer_A is discussed in the following sections. 15.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TAR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TAR can be read or written with software.
Page 447: Starting The Timer
Timer_A Operation 15.2.2 Starting the Timer The timer may be started, or restarted in the following ways: The timer counts when MCx > 0 and the clock source is active. When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TACCR0.
Page 448 Timer_A Operation Up Mode The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly counts up to the value of compare register TACCR0, which defines the period, as shown in Figure 15−2. The number of timer counts in the period is TACCR0+1.
Page 449 Timer_A Operation Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in Figure 15−4. The capture/compare register TACCR0 works the same way as the other capture/compare registers. Figure 15−4. Continuous Mode 0FFFFh The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero.
Page 450 Timer_A Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TACCRx register in the interrupt service routine.
Page 451 Timer_A Operation Up/Down Mode The up/down mode is used if the timer period must be different from 0FFFFh counts, and if symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare register TACCR0 and back down to zero, as shown in Figure 15−7.
Page 452 Timer_A Operation Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, and counting in the down direction, the timer continues its descent until it reaches zero. The value in TACCR0 is latched into TACL0 immediately, however, the new period takes effect after the counter counts down to zero.
Page 453: Capture/Compare Blocks
Timer_A Operation 15.2.4 Capture/Compare Blocks Three or five identical capture/compare blocks, TACCRx, are present in Timer_A. Any of the blocks may be used to capture the timer data, or to generate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is used to record time events.
Page 454 Timer_A Operation Figure 15−11.Capture Cycle Idle Capture Capture Read Read Capture Capture Taken Taken Taken Capture Capture Capture Read and No Capture Capture Clear Bit COV in Register TACCTLx Second Capture Idle Taken COV = 1 Capture Capture Initiated by Software Captures can be initiated by software.
Page 455: Output Unit
Timer_A Operation 15.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. Output Modes The output modes are defined by the OUTMODx bits and are described in Table 15−2.
Page 456 Timer_A Operation Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode. An example is shown in Figure 15−12 using TACCR0 and TACCR1. Figure 15−12.
Page 457 Timer_A Operation Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCR0 values, depending on the output mode. An example is shown in Figure 15−13 using TACCR0 and TACCR1. Figure 15−13. Output Example—Timer in Continuous Mode 0FFFFh TACCR0 TACCR1...
Page 458 Timer_A Operation Output Example—Timer in Up/Down Mode The OUTx signal changes when the timer equals TACCRx in either count direction and when the timer equals TACCR0, depending on the output mode. An example is shown in Figure 15−14 using TACCR0 and TACCR2. Figure 15−14.
Page 459: Timer_A Interrupts
Timer_A Operation 15.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: TACCR0 interrupt vector for TACCR0 CCIFG TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register.
Page 460 Timer_A Operation TAIV Software Example The following software example shows the recommended use of TAIV and the handling overhead. The TAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 461: Timer_A Registers
Timer_A Registers 15.3 Timer_A Registers The Timer_A registers are listed in Table 15−3 and Table 15−4. Table 15−3.Timer_A3 Registers Register Short Form Register Type Address Initial State Timer_A control TACTL/ Read/write 0160h Reset with POR Timer0_A3 Control TA0CTL Timer_A counter TAR/ Read/write 0170h...
Page 462 Timer_A Registers TACTL, Timer_A Control Register Unused TASSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused TACLR TAIE TAIFG rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) w−(0) rw−(0) rw−(0) Unused Bits Unused 15-10 TASSELx Bits Timer_A clock source select TACLK ACLK SMCLK Inverted TACLK Bits...
Page 463 Timer_A Registers TAR, Timer_A Register TARx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) TARx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Bits Timer_A register. The TAR register is the count of Timer_A. TARx 15-0 TACCRx, Timer_A Capture/Compare Register x TACCRx rw−(0) rw−(0)
Page 464 Timer_A Registers TACCTLx, Capture/Compare Control Register CCISx SCCI Unused rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) OUTMODx CCIE CCIFG rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Capture mode 15-14 No capture Capture on rising edge Capture on falling edge Capture on both rising and falling edges CCISx Capture/compare input select.
Page 465 Timer_A Registers CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. Interrupt disabled Interrupt enabled Bit 3 Capture/compare input. The selected input signal can be read by this bit. Bit 2 Output. For output mode 0, this bit directly controls the state of the output. Output low Output high Bit 1...
Page 466 15-24 Timer_A...
Page 467: Timer_B
Chapter 16 Timer_B Timer_B is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes the operation of the Timer_B of the MSP430x4xx device family. Topic Page 16.1 Timer_B Introduction ......... 16-2 16.2 Timer_B Operation .
Page 468: Timer_B Introduction
Timer_B Introduction 16.1 Timer_B Introduction Timer_B is a 16-bit timer/counter with three or seven capture/compare registers. Timer_B can support multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Page 469 Timer_B Introduction Figure 16−1. Timer_B Block Diagram Timer Block Timer Clock TBSSELx 16−bit Timer TBCLK Divider Count EQU0 1/2/4/8 Mode ACLK Clear 10 12 16 SMCLK CNTLx TBCLR TBCLGRPx Set TBIFG Group Load Logic CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 CCISx logic...
Page 470: Timer_B Operation
Timer_B Operation 16.2 Timer_B Operation The Timer_B module is configured with user software. The setup and operation of Timer_B is discussed in the following sections. 16.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TBR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TBR can be read or written with software.
Page 471: Starting The Timer
Timer_B Operation 16.2.2 Starting the Timer The timer may be started or restarted in the following ways: The timer counts when MCx > 0 and the clock source is active. When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBCL0.
Page 472 Timer_B Operation Up Mode The up mode is used if the timer period must be different from TBR counts. (max) The timer repeatedly counts up to the value of compare latch TBCL0, which defines the period, as shown in Figure 16−2. The number of timer counts in the period is TBCL0+1.
Page 473 Timer_B Operation Continuous Mode In continuous mode the timer repeatedly counts up to TBR and restarts (max) from zero as shown in Figure 16−4. The compare latch TBCL0 works the same way as the other capture/compare registers. Figure 16−4. Continuous Mode TBR (max) The TBIFG interrupt flag is set when the timer counts from TBR to zero.
Page 474 Timer_B Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TBCLx latch in the interrupt service routine.
Page 475 Timer_B Operation Up/Down Mode The up/down mode is used if the timer period must be different from TBR (max) counts, and if a symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare latch TBCL0, and back down to zero, as shown in Figure 16−7.
Page 476 Timer_B Operation Changing the Value of Period Register TBCL0 When changing TBCL0 while the timer is running and counting in the down direction, and when the TBCL0 load event is immediate, the timer continues its descent until it reaches zero. The value in TBCCR0 is latched into TBCL0 immediately;...
Page 477: Capture/Compare Blocks
Timer_B Operation 16.2.4 Capture/Compare Blocks Three or seven identical capture/compare blocks, TBCCRx, are present in Timer_B. Any of the blocks may be used to capture the timer data or to generate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is used to record time events.
Page 478 Timer_B Operation Figure 16−11.Capture Cycle Idle Capture Capture Read Read Capture Capture Taken Taken Taken Capture Capture Capture Read and No Capture Capture Clear Bit COV in Register TBCCTLx Second Capture Idle Taken COV = 1 Capture Capture Initiated by Software Captures can be initiated by software.
Page 479 Timer_B Operation Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to the timer value in compare mode. TBCLx is buffered by TBCCRx. The buffered compare latch gives the user control over when a compare period updates. The user cannot directly access TBCLx.
Page 480: Output Unit
Timer_B Operation 16.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. The TBOUTH pin function can be used to put all Timer_B outputs into a high-impedance state.
Page 481 Timer_B Operation Output Example—Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode. An example is shown in Figure 16−12 using TBCL0 and TBCL1. Figure 16−12.
Page 482 Timer_B Operation Output Example—Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, An example is shown in Figure 16−13 using TBCL0 and TBCL1. Figure 16−13. Output Example—Timer in Continuous Mode TBR (max) TBCL0 TBCL1...
Page 483 Timer_B Operation Output Example − Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode. An example is shown in Figure 16−14 using TBCL0 and TBCL3. Figure 16−14.
Page 484: Timer_B Interrupts
Timer_B Operation 16.2.6 Timer_B Interrupts Two interrupt vectors are associated with the 16-bit Timer_B module: TBCCR0 interrupt vector for TBCCR0 CCIFG TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured in the associated TBCCRx register.
Page 485 Timer_B Operation TBIV, Interrupt Handler Examples The following software example shows the recommended use of TBIV and the handling overhead. The TBIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU clock cycles for each instruction.
Page 486: Timer_B Registers
Timer_B Registers 16.3 Timer_B Registers The Timer_B registers are listed in Table 16−5. Table 16−5.Timer_B Registers Register Short Form Register Type Address Initial State Timer_B control TBCTL Read/write 0180h Reset with POR Timer_B counter Read/write 0190h Reset with POR Timer_B capture/compare control 0 TBCCTL0 Read/write 0182h...
Page 487 Timer_B Registers Timer_B Control Register TBCTL Unused TBCLGRPx CNTLx Unused TBSSELx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused TBCLR TBIE TBIFG rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) w−(0) rw−(0) rw−(0) Unused Bit 15 Unused TBCLGRP TBCLx group 14-13 Each TBCLx latch loads independently TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update)
Page 488 Timer_B Registers Unused Bit 3 Unused TBCLR Bit 2 Timer_B clear. Setting this bit resets TBR, the clock divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero. TBIE Bit 1 Timer_B interrupt enable. This bit enables the TBIFG interrupt request. Interrupt disabled Interrupt enabled TBIFG...
Page 489 Timer_B Registers TBCCRx, Timer_B Capture/Compare Register x TBCCRx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) TBCCRx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Bits Timer_B capture/compare register. TBCCRx 15-0 Compare mode: Compare data is written to each TBCCRx and automatically transferred to TBCLx.
Page 490 Timer_B Registers TBCCTLx, Capture/Compare Control Register CCISx CLLDx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) OUTMODx CCIE CCIFG rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Capture mode 15-14 No capture Capture on rising edge Capture on falling edge Capture on both rising and falling edges CCISx Capture/compare input select.
Page 491 Timer_B Registers CCIE Bit 4 Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. Interrupt disabled Interrupt enabled Bit 3 Capture/compare input. The selected input signal can be read by this bit. Bit 2 Output. For output mode 0, this bit directly controls the state of the output. Output low Output high Bit 1...
Page 492 Timer_B Registers TBIV, Timer_B Interrupt Vector Register TBIVx r−(0) r−(0) r−(0) Bits Timer_B interrupt vector value TBIVx 15-0 Interrupt Priority TBIV Contents Interrupt Source Interrupt Flag No interrupt pending − Capture/compare 1 TBCCR1 CCIFG Highest Capture/compare 2 TBCCR2 CCIFG † Capture/compare 3 TBCCR3 CCIFG †...
Page 493: Usart Peripheral Interface, Uart Mode
Chapter 17 USART Peripheral Interface, UART Mode universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. USART0 is implemented on the MSP430x42x and MSP430x43x devices. In addition to USART0, the MSP430x44x devices implement a second identical USART module, USART1.
Page 494: Usart Introduction: Uart Mode
USART Introduction: UART Mode 17.1 USART Introduction: UART Mode In asynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UART mode is selected when the SYNC bit is cleared. UART mode features include: 7- or 8-bit data with odd, even, or non-parity Independent transmit and receive shift registers Separate transmit and receive buffer registers...
Page 495 USART Introduction: UART Mode Figure 17−1. USART Block Diagram: UART Mode SWRST URXEx* URXEIE URXWIE SYNC= 0 URXIFGx* Receive Control Receive Status Receiver Buffer UxRXBUF LISTEN SYNC SOMI RXERR RXWAKE Receiver Shift Register URXD SSEL1 SSEL0 CHAR PENA UCLKS UCLKI Baud−Rate Generator ACLK Prescaler/Divider UxBRx...
Page 496: Usart Operation: Uart Mode
USART Operation: UART Mode 17.2 USART Operation: UART Mode In UART mode, the USART transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USART. The transmit and receive functions use the same baud rate frequency.
Page 497: Asynchronous Communication Formats
USART Operation: UART Mode 17.2.3 Asynchronous Communication Formats When two devices communicate asynchronously, the idle-line format is used for the protocol. When three or more devices communicate, the USART supports the idle-line and address-bit multiprocessor communication formats. Idle-Line Multiprocessor Format When MM = 0, the idle-line multiprocessor format is selected.
Page 498 USART Operation: UART Mode The URXWIE bit is used to control data reception in the idle-line multiprocessor format. When the URXWIE bit is set, all non-address characters are assembled but not transferred into the UxRXBUF, and interrupts are not generated. When an address character is received, the receiver is temporarily activated to transfer the character to UxRXBUF and sets the URXIFGx interrupt flag.
Page 499 USART Operation: UART Mode Address Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 17−4. The first character in a block of characters carries a set address bit which indicates that the character is an address.
Page 500 USART Operation: UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time t (approximately 300 ns) τ will be ignored. See the device-specific data sheet for parameters. When a low period on URXDx exceeds t a majority vote is taken for the start τ...
Page 501: Usart Receive Enable
USART Operation: UART Mode 17.2.4 USART Receive Enable The receive enable bit, URXEx, enables or disables data reception on URXDx as shown in Figure 17−5. Disabling the USART receiver stops the receive operation following completion of any character currently being received or immediately if no receive operation is active.
Page 502: Usart Transmit Enable
USART Operation: UART Mode 17.2.5 USART Transmit Enable When UTXEx is set, the UART transmitter is enabled. Transmission is initiated by writing data to UxTXBUF. The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty, and transmission begins.
Page 503: Usart Baud Rate Generation
USART Operation: UART Mode 17.2.6 USART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non-standard source frequencies. The baud rate generator uses one prescaler/divider and a modulator as shown in Figure 17−7. This combination supports fractional divisors for baud rate generation.
Page 504 USART Operation: UART Mode Baud Rate Bit Timing The first stage of the baud rate generator is the 16-bit counter and comparator. At the beginning of each bit transmitted or received, the counter is loaded with INT(N/2) where N is the value stored in the combination of UxBR0 and UxBR1. The counter reloads INT(N/2) for each bit period half-cycle, giving a total bit period of N BRCLKs.
Page 505 USART Operation: UART Mode Transmit Bit Timing The timing for each character is the sum of the individual bit timings. By modulating each bit, the cumulative bit error is reduced. The individual bit error can be calculated by: Error [%] + baud rate ( j ) 1 ) UxBR ) S * ( j ) 1 )
Page 506 USART Operation: UART Mode Receive Bit Timing Receive timing consists of two error sources. The first is the bit-to-bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USART. Figure 17−9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud-rate clock.
Page 507 USART Operation: UART Mode For example, the receive errors for the following conditions are calculated: Baud rate = 2400 BRCLK = 32,768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.65 UxMCTL = 6B:m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1 and m0 = 1 The LSB of UxMCTL is used first.
Page 508 USART Operation: UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in Table 17−2 for a 32,768-Hz watch crystal (ACLK) and a typical 1,048,576-Hz SMCLK. The receive error is the accumulated time versus the ideal scanning time in the middle of each bit.
Page 509: Usart Interrupts
USART Operation: UART Mode 17.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set.
Page 510 USART Operation: UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1.
Page 511 USART Operation: UART Mode Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. The recommended usage of the receive-start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low-power mode operation.
Page 512 USART Operation: UART Mode Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time t τ (approximately 300 ns) will be ignored by the USART and no interrupt request will be generated as shown in Figure 17−12.
Page 513: Usart Registers: Uart Mode
USART Registers: UART Mode 17.3 USART Registers: UART Mode Table 17−3 lists the registers for all devices implementing a USART module. Table 17−4 applies only to devices with a second USART module, USART1. Table 17−3.USART0 Control and Status Registers Register Short Form Register Type Address Initial State...
Page 514 USART Registers: UART Mode UxCTL, USART Control Register PENA CHAR LISTEN SYNC SWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 PENA Bit 7 Parity enable Parity disabled. Parity enabled. Parity bit is generated (UTXDx) and expected (URXDx). In address-bit multiprocessor mode, the address bit is included in the parity calculation.
Page 515 USART Registers: UART Mode UxTCTL, USART Transmit Control Register Unused CKPL SSELx URXSE TXWAKE Unused TXEPT rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 Unused Bit 7 Unused CKPL Bit 6 Clock polarity select UCLKI = UCLK UCLKI = inverted UCLK SSELx Bits Source select.
Page 516 USART Registers: UART Mode UxRCTL, USART Receive Control Register URXEIE URXWIE RXWAKE RXERR rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Bit 7 Framing error flag No error Character received with low stop bit Bit 6 Parity error flag. When PENA = 0, PE is read as 0. No error Character received with parity error Bit 5...
Page 517 USART Registers: UART Mode UxBR0, USART Baud Rate Control Register 0 UxBR1, USART Baud Rate Control Register 1 The valid baud-rate control range is 3 ≤ UxBR < 0FFFFh, where UxBRx UxBR = {UxBR1+UxBR0}. Unpredictable receive and transmit timing occurs if UxBR < 3. UxMCTL, USART Modulation Control Register UxMCTLx Bits...
Page 518 USART Registers: UART Mode UxRXBUF, USART Receive Buffer Register UxRXBUFx Bits The receive-data buffer is user accessible and contains the last received 7−0 character from the receive shift register. Reading UxRXBUF resets the receive-error bits, the RXWAKE bit, and URXIFGx. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset.
Page 519 USART Registers: UART Mode ME1, Module Enable Register 1 UTXE0 URXE0 rw−0 rw−0 UTXE0 Bit 7 USART0 transmit enable. This bit enables the transmitter for USART0. Module not enabled Module enabled URXE0 Bit 6 USART0 receive enable. This bit enables the receiver for USART0. Module not enabled Module enabled Bits...
Page 520 USART Registers: UART Mode IE1, Interrupt Enable Register 1 UTXIE0 URXIE0 rw−0 rw−0 UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. Interrupt not enabled Interrupt enabled URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. Interrupt not enabled Interrupt enabled Bits...
Page 521 USART Registers: UART Mode IFG1, Interrupt Flag Register 1 UTXIFG0 URXIFG0 rw−1 rw−0 UTXIFG0 Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. No interrupt pending Interrupt pending URXIFG0 Bit 6 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character.
Page 522 17-30 USART Peripheral Interface, UART Mode...
Page 523: Usart Peripheral Interface, Spi Mode
Chapter 18 USART Peripheral Interface, SPI Mode universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. USART0 is implemented on the MSP430x42x and MSP430x43x devices.
Page 524: Usart Introduction: Spi Mode
USART Introduction: SPI Mode 18.1 USART Introduction: SPI Mode In synchronous mode, the USART connects the MSP430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared. SPI mode features include: 7- or 8-bit data length 3-pin and 4-pin SPI operation...
Page 525 USART Introduction: SPI Mode Figure 18−1. USART Block Diagram: SPI Mode SWRST USPIEx* URXEIE URXWIE SYNC= 1 URXIFGx* Receive Control Receive Status Receiver Buffer UxRXBUF LISTEN SYNC SOMI RXERR RXWAKE Receiver Shift Register URXD SSEL1 SSEL0 CHAR PENA UCLKS UCLKI Baud−Rate Generator ACLK Prescaler/Divider UxBRx...
Page 526: Usart Operation: Spi Mode
USART Operation: SPI Mode 18.2 USART Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, STE, is provided as to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: SIMO Slave in, master out...
Page 527: Master Mode
USART Operation: SPI Mode 18.2.2 Master Mode Figure 18−2. USART Master and External Slave MASTER SLAVE SIMO SIMO Receive Buffer UxRXBUF Transmit Buffer UxTXBUF SPI Receive Buffer Px.x Port.x SOMI SOMI Receive Shift Register Transmit Shift Register Data Shift Register (DSR) SCLK UCLK MSP430 USART...
Page 528: Slave Mode
USART Operation: SPI Mode 18.2.3 Slave Mode Figure 18−3. USART Slave and External Master MASTER SLAVE SIMO SIMO SPI Receive Buffer Transmit Buffer UxTXBUF Receive Buffer UxRXBUF Px.x Port.x SOMI SOMI Data Shift Register DSR Transmit Shift Register Receive Shift Register SCLK UCLK COMMON SPI...
Page 529: Spi Enable
USART Operation: SPI Mode 18.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USART in SPI mode. When USPIEx = 0, the USART stops operation after the current transfer completes, or immediately if no operation is active. A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated.
Page 530 USART Operation: SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 18−6 and Figure 18−7. When USPIEx = 0, UCLK is disabled from shifting data into the RX shift register. Figure 18−6. SPI Master Receive-Enable State Diagram No Data Written USPIEx = 0 Not Completed...
Page 531: Serial Clock Control
USART Operation: SPI Mode 18.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Figure 18−8. When MM = 0, the USART clock is provided on the UCLK pin by the master and, the baud rate generator is not used and the SSELx bits are don’t care.
Page 532 USART Operation: SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART. Timing for each case is shown in Figure 18−9. Figure 18−9. USART SPI Timing Cycle# CKPH CKPL UCLK...
Page 533: Spi Interrupts
USART Operation: SPI Mode 18.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set.
Page 534 USART Operation: SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF as shown in Figure 18−11 and Figure 18−12. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1.
Page 535: Usart Registers: Spi Mode
USART Registers: SPI Mode 18.3 USART Registers: SPI Mode Table 18−1 lists the registers for all devices implementing a USART module. Table 18−2 applies only to devices with a second USART module, USART1. Table 18−1.USART0 Control and Status Registers Register Short Form Register Type Address Initial State...
Page 536 USART Registers: SPI Mode UxCTL, USART Control Register † Unused Unused CHAR LISTEN SYNC SWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 Unused Bits Unused 7−6 † Bit 5 I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1. SPI mode C mode CHAR...
Page 537 USART Registers: SPI Mode UxTCTL, USART Transmit Control Register CKPH CKPL SSELx Unused Unused TXEPT rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 CKPH Bit 7 Clock phase select. Data is changed on the first UCLK edge and captured on the following edge.
Page 538 USART Registers: SPI Mode UxRCTL, USART Receive Control Register Unused Unused Unused Unused Unused Unused rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Bit 7 Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode. No conflict detected A negative edge occurred on STE, indicating bus conflict Undefined...
Page 539 USART Registers: SPI Mode UxBR0, USART Baud Rate Control Register 0 UxBR1, USART Baud Rate Control Register 1 UxBRx The baud-rate generator uses the content of {UxBR1+UxBR0} to set the baud rate. Unpredictable SPI operation occurs if UxBR < 2. UxMCTL, USART Modulation Control Register UxMCTLx Bits...
Page 540 USART Registers: SPI Mode UxRXBUF, USART Receive Buffer Register UxRXBUFx Bits The receive-data buffer is user accessible and contains the last received 7−0 character from the receive shift register. Reading UxRXBUF resets the OE bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset.
Page 541 USART Registers: SPI Mode ME1, Module Enable Register 1 USPIE0 rw−0 Bit 7 This bit may be used by other modules. See device-specific data sheet. USPIE0 Bit 6 USART0 SPI enable. This bit enables the SPI mode for USART0. Module not enabled Module enabled Bits These bits may be used by other modules.
Page 542 USART Registers: SPI Mode IE1, Interrupt Enable Register 1 UTXIE0 URXIE0 rw−0 rw−0 UTXIE0 Bit 7 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. Interrupt not enabled Interrupt enabled URXIE0 Bit 6 USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. Interrupt not enabled Interrupt enabled Bits...
Page 543 USART Registers: SPI Mode IFG1, Interrupt Flag Register 1 UTXIFG0 URXIFG0 rw−1 rw−0 UTXIFG0 Bit 7 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. No interrupt pending Interrupt pending URXIFG0 Bit 6 USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character.
Page 544 18-22 USART Peripheral Interface, SPI Mode...
Page 545: Universal Serial Communication Interface, Uart Mode
Chapter 19 Universal Serial Communication Interface, UART Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. Topic Page 19.1 USCI Overview ..........19-2 19.2 USCI Introduction: UART Mode .
Page 546: Usci Overview
USCI Overview 19.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers.
Page 547: Usci Introduction: Uart Mode
USCI Introduction: UART Mode 19.2 USCI Introduction: UART Mode In asynchronous mode, the USCI_Ax modules connect the MSP430 to an external system via two external pins, UCAxRXD and UCAxTXD. UART mode is selected when the UCSYNC bit is cleared. UART mode features include: 7- or 8-bit data with odd, even, or non-parity Independent transmit and receive shift registers Separate transmit and receive buffer registers...
Page 548 USCI Introduction: UART Mode Figure 19−1. USCI_Ax Block Diagram: UART Mode (UCSYNC = 0) UCRXEIE UCRXERR Error Flags UCMODEx UCSPB UCDORM UCPE UCRXBRKIE UCFE UCOE Set Flags Receive State Machine Set RXIFG Set UC0RXIFG Set UCBRK Set UCADDR/UCIDLE UCIRRXPL UCIRRXFLx UCIRRXFE Receive Buffer UC0RXBUF UCIREN...
Page 549: Usci Operation: Uart Mode
USCI Operation: UART Mode 19.3 USCI Operation: UART Mode In UART mode, the USCI transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USCI. The transmit and receive functions use the same baud rate frequency.
Page 550: Asynchronous Communication Formats
USCI Operation: UART Mode 19.3.3 Asynchronous Communication Formats When two devices communicate asynchronously, no multiprocessor format is required for the protocol. When three or more devices communicate, the USCI supports the idle-line and address-bit multiprocessor communication formats. Idle-Line Multiprocessor Format When UCMODEx = 01, the idle-line multiprocessor format is selected.
Page 551 USCI Operation: UART Mode The UCDORM bit is used to control data reception in the idle-line multiprocessor format. When UCDORM = 1, all non-address characters are assembled but not transferred into the UCAxRXBUF, and interrupts are not generated. When an address character is received, the character is transferred into UCAxRXBUF, UCAxRXIFG is set, and any applicable error flag is set when UCRXEIE = 1.
Page 552 USCI Operation: UART Mode Address Bit Multiprocessor Format When UCMODEx = 10, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 19−4. The first character in a block of characters carries a set address bit which indicates that the character is an address.
Page 553 USCI Operation: UART Mode Figure 19−4. Address Bit Multiprocessor Format Blocks of Characters UCAxTXD/UCAxRXD Idle Periods of No Significance UCAxTXD/UCAxRXD Expanded UCAxTXD/UCAxRXD Address SP ST Data Data AD Bit Is 0 for First Character Within Block Data Within Block. Is an Address. AD Bit Is 1 Idle Time Is of No Significance Break Reception and Generation When UCMODEx = 00, 01, or 10 the receiver detects a break when all data,...
Page 554: Automatic Baud Rate Detection
USCI Operation: UART Mode 19.3.4 Automatic Baud Rate Detection When UCMODEx = 11 UART mode with automatic baud rate detection is selected. For automatic baud rate detection, a data frame is preceded by a synchronization sequence that consists of a break and a synch field. A break is detected when 11 or more continuous zeros (spaces) are received.
Page 555 USCI Operation: UART Mode When a break/synch field is received, user software must reset UCDORM to continue receiving data. If UCDORM remains set, only the character after the next reception of a break/synch field will be received. The UCDORM bit is not modified by the USCI hardware automatically.
Page 556: Irda Encoding And Decoding
USCI Operation: UART Mode 19.3.5 IrDA Encoding and Decoding When UCIREN is set the IrDA encoder and decoder are enabled and provide hardware bit shaping for IrDA communication. IrDA Encoding The encoder sends a pulse for every zero bit in the transmit bit stream coming from the UART as shown in Figure 19−7.
Page 557: Automatic Error Detection
USCI Operation: UART Mode 19.3.6 Automatic Error Detection Glitch suppression prevents the USCI from being accidentally started. Any pulse on UCAxRXD shorter than the deglitch time t (approximately 150 ns) τ will be ignored. See the device-specific data sheet for parameters. When a low period on UCAxRXD exceeds t a majority vote is taken for the τ...
Page 558: Usci Receive Enable
USCI Operation: UART Mode error flags except UCOE if UCAxRXBUF was overwritten between the read access to UCAxSTAT and to UCAxRXBUF. So the UCOE flag should be checked after reading UCAxRXBUF to detect this condition. Note, in this case the UCRXERR flag is not set. 19.3.7 USCI Receive Enable The USCI module is enabled by clearing the UCSWRST bit and the receiver is ready and in an idle state.
Page 559: Usci Transmit Enable
USCI Operation: UART Mode Figure 19−9. Glitch Suppression, USCI Activated Majority Vote Taken URXDx URXS τ 19.3.8 USCI Transmit Enable The USCI module is enabled by clearing the UCSWRST bit and the transmitter is ready and in an idle state. The transmit baud rate generator is ready but is not clocked nor producing any clocks.
Page 560 USCI Operation: UART Mode Figure 19−10. BITCLK Baud Rate Timing with UCOS16 = 0 (m= 0) Majority Vote: (m= 1) Bit Start BRCLK N/2−1 N/2−2 N/2−1 Counter N/2−1 N/2−2 N/2−1 BITCLK N EVEN : INT(N/2) INT(N/2) + m(= 0) N ODD : INT(N/2) + R(= 1) INT(N/2) + m(= 1) Bit Period m: corresponding modulation bit...
Page 561 USCI Operation: UART Mode Oversampling Baud Rate Generation The oversampling mode is selected when UCOS16 = 1. This mode supports sampling a UART bit stream with higher input clock frequencies. This results in majority votes that are always 1/16 of a bit clock period apart. This mode also easily supports IrDA pulses with a 3/16 bit-time when the IrDA encoder and decoder are enabled.
Page 562: Setting A Baud Rate
USCI Operation: UART Mode 19.3.10 Setting a Baud Rate For a given BRCLK clock source, the baud rate used determines the required division factor N: BRCLK Baudrate The division factor N is often a non-integer value thus at least one divider and one modulator stage is used to meet the factor as closely as possible.
Page 563: Transmit Bit Timing
USCI Operation: UART Mode 19.3.11 Transmit Bit Timing The timing for each character is the sum of the individual bit timings. Using the modulation features of the baud rate generator reduces the cumulative bit error. The individual bit error can be calculated using the following steps. Low−Frequency Baud Rate Mode Bit Timing In low-frequency mode, calculate the length of bit i T [i] based on the...
Page 564: Receive Bit Timing
USCI Operation: UART Mode 19.3.12 Receive Bit Timing Receive timing error consists of two error sources. The first is the bit-to-bit timing error similar to the transmit bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USCI module.
Page 565: Typical Baud Rates And Errors
USCI Operation: UART Mode For the oversampling baud rate mode the sampling time t [i] of bit i is bit,RX calculated by: [i] + t bit,RX SYNC bit,RX UCBRSx [ i ] @ UCBRx ) 8 ) m UCBRSx UCBRFx BRCLK where: [i] +...
Page 566 USCI Operation: UART Mode Table 19−4.Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 BRCLK Baud Frequency Rate UCBRx UCBRSx UCBRFx Max TX Error [%] Max RX Error [%] [Hz] [Baud] 32,768 1200 −2.8 −5.9 32,768 2400 −4.8 −9.7 32,768 4800 −12.1...
Page 567 USCI Operation: UART Mode Table 19−4.Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 (Continued) BRCLK Baud Frequency Rate UCBRx UCBRSx UCBRFx Max TX Error [%] Max RX Error [%] [Hz] [Baud] 16,000,000 9600 1666 −0.05 0.05 −0.05 16,000,000 19200 −0.1 0.05...
Page 568 USCI Operation: UART Mode Table 19−5.Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1 BRCLK Baud frequency Rate UCBRx UCBRSx UCBRFx Max. TX Error [%] Max. RX Error [%] [Hz] [Baud] 1,048,576 9600 −2.3 −2.2 1,048,576 19200 −4.6 −5.0 1,000,000 9600 −1.8...
Page 569: Using The Usci Module In Uart Mode With Low-Power Modes
USCI Operation: UART Mode 19.3.14 Using the USCI Module in UART Mode with Low-Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source.
Page 570 USCI Operation: UART Mode USCI Interrupt Usage USCI_Ax and USCI_Bx share the same interrupt vectors. The receive interrupt flags UCAxRXIFG and UCBxRXIFG are routed to one interrupt vector, the transmit interrupt flags UCAxTXIFG and UCBxTXIFG share another interrupt vector. Shared Interrupt Vectors Software Example The following software example shows an extract of an interrupt service routine to handle data receive interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode.
Page 571: Usci Registers: Uart Mode
USCI Registers: UART Mode 19.4 USCI Registers: UART Mode The USCI registers applicable in UART mode are listed in Table 19−6 and Table 19−7. Table 19−6.USCI_A0 Control and Status Registers Register Short Form Register Type Address Initial State USCI_A0 control register 0 UCA0CTL0 Read/write 060h...
Page 572 USCI Registers: UART Mode UCAxCTL0, USCI_Ax Control Register 0 UCPEN UCPAR UCMSB UC7BIT UCSPB UCMODEx UCSYNC=0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 UCPEN Bit 7 Parity enable Parity disabled. Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD).
Page 573 USCI Registers: UART Mode UCAxCTL1, USCI_Ax Control Register 1 UCSSELx UCRXEIE UCBRKIE UCDORM UCTXADDR UCTXBRK UCSWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 UCSSELx Bits USCI clock source select. These bits select the BRCLK source clock. UCLK ACLK SMCLK SMCLK UCRXEIE Bit 5...
Page 574 USCI Registers: UART Mode UCAxBR0, USCI_Ax Baud Rate Control Register 0 UCBRx UCAxBR1, USCI_Ax Baud Rate Control Register 1 UCBRx UCBRx Clock prescaler setting of the Baud rate generator. The 16-bit value of (UCAxBR0 + UCAxBR1 × 256) forms the prescaler value. UCAxMCTL, USCI_Ax Modulation Control Register UCBRFx UCBRSx...
Page 575 USCI Registers: UART Mode UCAxSTAT, USCI_Ax Status Register UCADDR UCLISTEN UCFE UCOE UCPE UCBRK UCRXERR UCBUSY UCIDLE rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 r−0 UCLISTEN Bit 7 Listen enable. The UCLISTEN bit selects loopback mode. Disabled Enabled. UCAxTXD is internally fed back to the receiver. UCFE Bit 6 Framing error flag...
Page 576 USCI Registers: UART Mode UCAxRXBUF, USCI_Ax Receive Buffer Register UCRXBUFx UCRXBUFx Bits The receive-data buffer is user accessible and contains the last received 7−0 character from the receive shift register. Reading UCAxRXBUF resets the receive-error bits, the UCADDR or UCIDLE bit, and UCAxRXIFG. In 7-bit data mode, UCAxRXBUF is LSB justified and the MSB is always reset.
Page 577 USCI Registers: UART Mode UCAxIRTCTL, USCI_Ax IrDA Transmit Control Register UCIR UCIRTXPLx UCIREN TXCLK rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 UCIRTXPLx Bits Transmit pulse length = (UCIRTXPLx + 1) / (2 × f 7−2 Pulse Length t PULSE IRTXCLK UCIRTXCLK Bit 1...
Page 578 USCI Registers: UART Mode UCAxABCTL, USCI_Ax Auto Baud Rate Control Register Reserved UCDELIMx UCSTOE UCBTOE Reserved UCABDEN r−0 r−0 rw−0 rw−0 rw−0 rw−0 r−0 rw−0 Reserved Bits Reserved UCDELIMx Bits Break/synch delimiter length 5−4 1 bit time 2 bit times 3 bit times 4 bit times UCSTOE...
Page 579 USCI Registers: UART Mode IE2, Interrupt Enable Register 2 UCA0TXIE UCA0RXIE rw−0 rw−0 Bits These bits may be used by other modules. See device-specific data sheet. UCA0TXIE Bit 1 USCI_A0 transmit interrupt enable Interrupt disabled Interrupt enabled UCA0RXIE Bit 0 USCI_A0 receive interrupt enable Interrupt disabled Interrupt enabled...
Page 580 USCI Registers: UART Mode UC1IE, USCI_A1 Interrupt Enable Register Unused Unused Unused Unused UCA1TXIE UCA1RXIE rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Bits Unused Unused Bits These bits may be used by other USCI modules (see the device-specific data sheet). UCA1TXIE Bit 1 USCI_A1 transmit interrupt enable Interrupt disabled...
Page 581: Universal Serial Communication Interface, Spi Mode
Chapter 20 Universal Serial Communication Interface, SPI Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. Topic Page 20.1 USCI Overview .
Page 582: Usci Overview
USCI Overview 20.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers.
Page 583: Usci Introduction: Spi Mode
USCI Introduction: SPI Mode 20.2 USCI Introduction: SPI Mode In synchronous mode, the USCI connects the MSP430 to an external system via three or four pins: UCxSIMO, UCxSOMI, UCxCLK, and UCxSTE. SPI mode is selected when the UCSYNC bit is set and SPI mode (3-pin or 4-pin) is selected with the UCMODEx bits.
Page 584 USCI Introduction: SPI Mode Figure 20−1. USCI Block Diagram: SPI Mode Receive State Machine Set UCOE Set UCxRXIFG UCLISTEN UCMST Receive Buffer UCxRXBUF UCxSOMI Receive Shift Register UCMSB UC7BIT UCSSELx Bit Clock Generator UCCKPH UCCKPL UCxBRx UCxCLK ACLK Clock Direction, Prescaler/Divider Phase and Polarity SMCLK...
Page 585: Usci Operation: Spi Mode
USCI Operation: SPI Mode 20.3 USCI Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, UCxSTE, is provided to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: UCxSIMO Slave in, master out...
Page 586: Usci Initialization And Reset
USCI Operation: SPI Mode 20.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition. When set, the UCSWRST bit resets the UCxRXIE, UCxTXIE, UCxRXIFG, UCOE, and UCFE bits and sets the UCxTXIFG flag.
Page 587: Master Mode
USCI Operation: SPI Mode 20.3.3 Master Mode Figure 20−2. USCI Master and External Slave MASTER SLAVE UCxSIMO SIMO Receive Buffer Transmit Buffer SPI Receive Buffer UCxRXBUF UCxTXBUF Px.x UCxSTE Port.x SOMI SOMI Receive Shift Register Transmit Shift Register Data Shift Register (DSR) SCLK UCxCLK MSP430 USCI...
Page 588 USCI Operation: SPI Mode Four-Pin SPI Master Mode In 4-pin master mode, UCxSTE is used to prevent conflicts with another master and controls the master as described in Table 20−1. When UCxSTE is in the master-inactive state: UCxSIMO and UCxCLK are set to inputs and no longer drive the bus The error bit UCFE is set indicating a communication integrity violation to be handled by the user.
Page 589: Slave Mode
USCI Operation: SPI Mode 20.3.4 Slave Mode Figure 20−3. USCI Slave and External Master MASTER SLAVE SIMO UCxSIMO Transmit Buffer Receive Buffer SPI Receive Buffer UCxTXBUF UCxRXBUF Px.x UCxSTE Port.x SOMI SOMI Data Shift Register DSR Transmit Shift Register Receive Shift Register SCLK UCxCLK COMMON SPI...
Page 590: Spi Enable
USCI Operation: SPI Mode 20.3.5 SPI Enable When the USCI module is enabled by clearing the UCSWRST bit it is ready to receive and transmit. In master mode the bit clock generator is ready, but is not clocked nor producing any clocks. In slave mode the bit clock generator is disabled and the clock is provided by the master.
Page 591: Serial Clock Control
USCI Operation: SPI Mode 20.3.6 Serial Clock Control UCxCLK is provided by the master on the SPI bus. When UCMST = 1, the bit clock is provided by the USCI bit clock generator on the UCxCLK pin. The clock used to generate the bit clock is selected with the UCSSELx bits. When UCMST = 0, the USCI clock is provided on the UCxCLK pin by the master, the bit clock generator is not used, and the UCSSELx bits are don’t care.
Page 592: Using The Spi Mode With Low Power Modes
USCI Operation: SPI Mode 20.3.7 Using the SPI Mode with Low Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source.
Page 593 USCI Operation: SPI Mode USCI Interrupt Usage USCI_Ax and USCI_Bx share the same interrupt vectors. The receive interrupt flags UCAxRXIFG and UCBxRXIFG are routed to one interrupt vector, the transmit interrupt flags UCAxTXIFG and UCBxTXIFG share another interrupt vector. Shared Interrupt Vectors Software Example The following software example shows an extract of an interrupt service routine to handle data receive interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode.
Page 594: Usci Registers: Spi Mode
USCI Registers: SPI Mode 20.4 USCI Registers: SPI Mode The USCI registers applicable in SPI mode for USCI_A0 and USCI_B0 are listed in Table 20−2. Registers applicable in SPI mode for USCI_A1 and USCI_B1 are listed in Table 20−3. Table 20−2.USCI_A0 and USCI_B0 Control and Status Registers Register Short Form Register Type Address...
Page 595 USCI Registers: SPI Mode Table 20−3.USCI_A1 and USCI_B1 Control and Status Registers Register Short Form Register Type Address Initial State USCI_A1 control register 0 UCA1CTL0 Read/write 0D0h Reset with PUC USCI_A1 control register 1 UCA1CTL1 Read/write 0D1h 001h with PUC USCI_A1 Baud rate control register 0 UCA1BR0 Read/write...
Page 596 USCI Registers: SPI Mode UCAxCTL0, USCI_Ax Control Register 0 UCBxCTL0, USCI_Bx Control Register 0 UCCKPH UCCKPL UCMSB UC7BIT UCMST UCMODEx UCSYNC=1 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 UCCKPH Bit 7 Clock phase select. Data is changed on the first UCLK edge and captured on the following edge.
Page 597 USCI Registers: SPI Mode UCAxCTL1, USCI_Ax Control Register 1 UCBxCTL1, USCI_Bx Control Register 1 UCSSELx Unused UCSWRST † rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 ‡ † UCAxCTL1 (USCI_Ax) ‡ UCBxCTL1 (USCI_Bx) UCSSELx Bits USCI clock source select. These bits select the BRCLK source clock in master mode.
Page 598 USCI Registers: SPI Mode UCAxBR0, USCI_Ax Bit Rate Control Register 0 UCBxBR0, USCI_Bx Bit Rate Control Register 0 UCBRx − low byte UCAxBR1, USCI_Ax Bit Rate Control Register 1 UCBxBR1, USCI_Bx Bit Rate Control Register 1 UCBRx − high byte UCBRx Bit clock prescaler setting.
Page 599 USCI Registers: SPI Mode UCAxSTAT, USCI_Ax Status Register UCBxSTAT, USCI_Bx Status Register UCLISTEN UCFE UCOE Unused Unused Unused Unused UCBUSY † rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 ‡ † UCAxSTAT (USCI_Ax) ‡ UCBxSTAT (USCI_Bx) UCLISTEN Bit 7 Listen enable. The UCLISTEN bit selects loopback mode. Disabled Enabled.
Page 600 USCI Registers: SPI Mode UCAxRXBUF, USCI_Ax Receive Buffer Register UCBxRXBUF, USCI_Bx Receive Buffer Register UCRXBUFx UCRXBUFx Bits The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCxRXBUF resets the receive-error bits, and UCxRXIFG. In 7-bit data mode, UCxRXBUF is LSB justified and the MSB is always reset.
Page 601 USCI Registers: SPI Mode IE2, Interrupt Enable Register 2 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 Bits These bits may be used by other modules. See device-specific data sheet. UCB0TXIE Bit 3 USCI_B0 transmit interrupt enable Interrupt disabled Interrupt enabled UCB0RXIE Bit 2 USCI_B0 receive interrupt enable...
Page 602 USCI Registers: SPI Mode IFG2, Interrupt Flag Register 2 UCB0 UCB0 UCA0 UCA0 TXIFG RXIFG TXIFG RXIFG rw-1 rw-0 rw-1 rw-0 Bits These bits may be used by other modules. See device-specific data sheet. UCB0 Bit 3 USCI_B0 transmit interrupt flag. UCB0TXIFG is set when UCB0TXBUF is TXIFG empty.
Page 603 USCI Registers: SPI Mode UC1IE, USCI_A1/USCI_B1 Interrupt Enable Register Unused Unused Unused Unused UCB1TXIE UCB1RXIE UCA1TXIE UCA1RXIE rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Bits Unused Unused UCB1TXIE Bit 3 USCI_B1 transmit interrupt enable Interrupt disabled Interrupt enabled UCB1RXIE Bit 2 USCI_B1 receive interrupt enable Interrupt disabled...
Page 604 USCI Registers: SPI Mode UC1IFG, USCI_A1/USCI_B1 Interrupt Flag Register UCB1 UCB1 UCA1 UCA1 Unused Unused Unused Unused TXIFG RXIFG TXIFG RXIFG rw−0 rw−0 rw−0 rw−0 rw−1 rw−0 rw−1 rw−0 Bits Unused Unused UCB1 Bit 3 USCI_B1 transmit interrupt flag. UCB1TXIFG is set when UCB1TXBUF is TXIFG empty.
Page 605: Universal Serial Communication Interface, I2C Mode
Chapter 21 Universal Serial Communication Interface, C Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the I C mode. Topic Page 21.1 USCI Overview ..........21-2 21.2 USCI Introduction: I C Mode...
Page 606: Usci Overview
USCI Overview 21.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers.
Page 607: Usci Introduction: I2C Mode
USCI Introduction: I2C Mode 21.2 USCI Introduction: I C Mode In I C mode, the USCI module provides an interface between the MSP430 and C-compatible devices connected by way of the two-wire I C serial bus. External components attached to the I C bus serially transmit and/or receive serial data to/from the USCI module through the 2-wire I C interface.
Page 608 USCI Introduction: I2C Mode Figure 21−1. USCI Block Diagram: I C Mode UCA10 UCGCEN Own Address UC1OA UCxSDA Receive Shift Register Receive Buffer UC1RXBUF I2C State Machine Transmit Buffer UC1TXBUF Transmit Shift Register Slave Address UC1SA UCSLA10 UCxSCL UCSSELx Bit Clock Generator UCxBRx UC1CLK UCMST...
Page 609: Usci Operation: I2C Mode
USCI Operation: I2C Mode 21.3 USCI Operation: I C Mode The I C mode supports any slave or master I C-compatible device. Figure 21−2 shows an example of an I C bus. Each I C device is recognized by a unique address and can operate as either a transmitter or a receiver. A device connected to the I C bus can be considered as the master or the slave when performing data transfers.
Page 610: Usci Initialization And Reset
USCI Operation: I2C Mode 21.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition. To select I C operation the UCMODEx bits must be set to 11.
Page 611 USCI Operation: I2C Mode 21.3.2 I C Serial Data One clock pulse is generated by the master device for each data bit transferred. The I C mode operates with byte data. Data is transferred most significant bit first as shown in Figure 21−3. The first byte after a START condition consists of a 7-bit slave address and the R/W bit.
Page 612 USCI Operation: I2C Mode 21.3.3 I C Addressing Modes The I C mode supports 7-bit and 10-bit addressing modes. 7-Bit Addressing In the 7-bit addressing format, shown in Figure 21−5, the first byte is the 7-bit slave address and the R/W bit. The ACK bit is sent from the receiver after each byte.
Page 613 USCI Operation: I2C Mode 21.3.4 I C Module Operating Modes In I C mode the USCI module can operate in master transmitter, master receiver, slave transmitter, or slave receiver mode. The modes are discussed in the following sections. Time lines are used to illustrate the modes. Figure 21−8 shows how to interpret the time line figures.
Page 614 USCI Operation: I2C Mode Slave Mode The USCI module is configured as an I C slave by selecting the I C mode with UCMODEx = 11 and UCSYNC = 1 and clearing the UCMST bit. Initially the USCI module must be configured in receiver mode by clearing the UCTR bit to receive the I C address.
Page 615 USCI Operation: I2C Mode Figure 21−9. I C Slave Transmitter Mode Reception of own SLA/R DATA DATA DATA address and transmission of data bytes UCTR= 1(Transmitter) Write data to UCBxTXBUF UCBxTXIFG= 0 UCSTTIFG= 1 UCBxTXIFG= 1 UCSTPIFG=? 0 UCBxTXIFG= 1 UCSTPIFG= 1 UCBxTXBUF discarded UCSTTIFG= 0...
Page 616 USCI Operation: I2C Mode C Slave Receiver Mode Slave receiver mode is entered when the slave address transmitted by the master is identical to its own address and a cleared R/W bit is received. In slave receiver mode, serial data bits received on SDA are shifted in with the clock pulses that are generated by the master device.
Page 617 USCI Operation: I2C Mode Figure 21−10. I C Slave Receiver Mode Reception of own SLA/W DATA DATA DATA P or S address and data bytes. All are acknowledged. UCBxRXIFG= 1 UCTR= 0(Receiver) UCSTTIFG= 1 Bus stalled UCSTPIFG= 0 (SCL held low) if UCBxRXBUF not read Refer to: Slave Transmitter...
Page 618 USCI Operation: I2C Mode C Slave 10-Bit Addressing Mode The 10-bit addressing mode is selected when UCA10 = 1 and is as shown in Figure 21−11. In 10-bit addressing mode, the slave is in receive mode after the full address is received. The USCI module indicates this by setting the UCSTTIFG flag while the UCTR bit is cleared.
Page 619 USCI Operation: I2C Mode Master Mode The USCI module is configured as an I C master by selecting the I C mode with UCMODEx = 11 and UCSYNC = 1 and setting the UCMST bit. When the master is part of a multi-master system, UCMM must be set and its own address must be programmed into the UCBxI2COA register.
Page 620 USCI Operation: I2C Mode Figure 21−12 illustrates the I C master transmitter operation. Figure 21−12. I C Master Transmitter Mode Successful SLA/W DATA DATA DATA transmission to a slave receiver 1) UCTR= 1(Transmitter) UCTXSTT= 0 UCTXSTP= 0 2) UCTXSTT= 1 UCBxTXIFG= 1 UCTXSTP= 1 UCBxTXIFG= 1...
Page 621 USCI Operation: I2C Mode C Master Receiver Mode After initialization, master receiver mode is initiated by writing the desired slave address to the UCBxI2CSA register, selecting the size of the slave address with the UCSLA10 bit, clearing UCTR for receiver mode, and setting UCTXSTT to generate a START condition.
Page 622 USCI Operation: I2C Mode Figure 21−13. I C Master Receiver Mode Successful DATA DATA DATA SLA/R reception from a slave transmitter UCTXSTP= 1 1) UCTR= 0 (Receiver) UCTXSTT = 0 UCBxRXIFG= 1 UCTXSTP= 0 2) UCTXSTT= 1 Next transfer started DATA SLA/W with a repeated start...
Page 623 USCI Operation: I2C Mode C Master 10-Bit Addressing Mode The 10-bit addressing mode is selected when UCSLA10 = 1 and is shown in Figure 21−14. Figure 21−14. I C Master 10-bit Addressing Mode Master Transmitter Successful 11110 xx/W SLA (2.) DATA DATA transmission to a...
Page 624 USCI Operation: I2C Mode Arbitration If two or more master transmitters simultaneously start a transmission on the bus, an arbitration procedure is invoked. Figure 21−15 illustrates the arbitration procedure between two devices. The arbitration procedure uses the data presented on SDA by the competing transmitters. The first master transmitter that generates a logic high is overruled by the opposing master generating a logic low.
Page 625 USCI Operation: I2C Mode 21.3.5 I C Clock Generation and Synchronization The I C clock SCL is provided by the master on the I C bus. When the USCI is in master mode, BITCLK is provided by the USCI bit clock generator and the clock source is selected with the UCSSELx bits.
Page 626 USCI Operation: I2C Mode Clock Stretching The USCI module supports clock stretching and also makes use of this feature as described in the operation mode sections. The UCSCLLOW bit can be used to observe if another device pulls SCL low while the USCI module already released SCL due to the following conditions: USCI is acting as master and a connected slave drives SCL low.
Page 627 USCI Operation: I2C Mode 21.3.7 USCI Interrupts in I C Mode Their are two interrupt vectors for the USCI module in I C mode. One interrupt vector is associated with the transmit and receive interrupt flags. The other interrupt vector is associated with the four state change interrupt flags. Each interrupt flag has its own interrupt enable bit.
Page 628 USCI Operation: I2C Mode Interrupt Vector Assignment USCI_Ax and USCI_Bx share the same interrupt vectors. In I C mode the state change interrupt flags UCSTTIFG, UCSTPIFG, UCNACKIFG, UCALIFG from USCI_Bx and UCAxRXIFG from USCI_Ax are routed to one interrupt vector. The I C transmit and receive interrupt flags UCBxTXIFG and UCBxRXIFG from USCI_Bx and UCAxTXIFG from USCI_Ax share another interrupt vector.
Page 629: Usci Registers: I2C Mode
USCI Registers: I2C Mode 21.4 USCI Registers: I C Mode The USCI registers applicable in I C mode for USCI_B0 are listed in Table 21−2 and for USCI_B1 in Table 21−3. Table 21−2.USCI_B0 Control and Status Registers Register Short Form Register Type Address Initial State USCI_B0 control register 0...
Page 630 USCI Registers: I2C Mode UCBxCTL0, USCI_Bx Control Register 0 UCA10 UCSLA10 UCMM Unused UCMST UCMODEx=11 UCSYNC=1 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 r−1 UCA10 Bit 7 Own addressing mode select Own address is a 7-bit address Own address is a 10-bit address UCSLA10 Bit 6 Slave addressing mode select...
Page 631 USCI Registers: I2C Mode UCBxCTL1, USCI_Bx Control Register 1 UCSSELx Unused UCTR UCTXNACK UCTXSTP UCTXSTT UCSWRST rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−1 UCSSELx Bits USCI clock source select. These bits select the BRCLK source clock. UCLKI ACLK SMCLK SMCLK Unused Bit 5 Unused...
Page 632 USCI Registers: I2C Mode UCBxBR0, USCI_Bx Baud Rate Control Register 0 UCBRx − low byte UCBxBR1, USCI_Bx Baud Rate Control Register 1 UCBRx − high byte UCBRx Bit clock prescaler setting. The 16-bit value of (UCBxBR0 + UCBxBR1 × 256} forms the prescaler value.
Page 633 USCI Registers: I2C Mode UCBxSTAT, USCI_Bx Status Register UCNACK Unused UCGC UCBBUSY UCSTPIFG UCSTTIFG UCALIFG SCLLOW rw−0 r−0 rw−0 r−0 rw−0 rw−0 rw−0 rw−0 Unused Bit 7 Unused. Bit 6 SCL low SCLLOW SCL is not held low SCL is held low UCGC Bit 5 General call address received.
Page 634 USCI Registers: I2C Mode UCBxRXBUF, USCI_Bx Receive Buffer Register UCRXBUFx UCRXBUFx Bits The receive-data buffer is user accessible and contains the last received 7−0 character from the receive shift register. Reading UCBxRXBUF resets UCBxRXIFG. UCBxTXBUF, USCI_Bx Transmit Buffer Register UCTXBUFx UCTXBUFx Bits The transmit data buffer is user accessible and holds the data waiting to...
Page 635 USCI Registers: I2C Mode UCBxI2COA, USCIBx I C Own Address Register UCGCEN I2COAx rw−0 rw−0 rw−0 I2COAx rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 UCGCEN Bit 15 General call response enable Do not respond to a general call Respond to a general call I2COAx Bits C own address.
Page 636 USCI Registers: I2C Mode UCBxI2CIE, USCI_Bx I C Interrupt Enable Register Reserved UCNACKIE UCSTPIE UCSTTIE UCALIE rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Reserved Bits Reserved 7−4 UCNACKIE Bit 3 Not-acknowledge interrupt enable Interrupt disabled Interrupt enabled UCSTPIE Bit 2 Stop condition interrupt enable Interrupt disabled Interrupt enabled...
Page 637 USCI Registers: I2C Mode IE2, Interrupt Enable Register 2 UCB0TXIE UCB0RXIE rw−0 rw−0 Bits These bits may be used by other modules (see the device-specific data sheet). UCB0TXIE Bit 3 USCI_B0 transmit interrupt enable Interrupt disabled Interrupt enabled UCB0RXIE Bit 2 USCI_B0 receive interrupt enable Interrupt disabled Interrupt enabled...
Page 638 USCI Registers: I2C Mode UC1IE, USCI_B1 Interrupt Enable Register Unused Unused Unused Unused UCB1TXIE UCB1RXIE rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Bits Unused Unused UCB1TXIE Bit 3 USCI_B1 transmit interrupt enable Interrupt disabled Interrupt enabled UCB1RXIE Bit 2 USCI_B1 receive interrupt enable Interrupt disabled Interrupt enabled Bits...
Page 639 Chapter 22 The OA is a general purpose operational amplifier. This chapter describes the OA. Three OA modules are implemented in the MSP430FG43x and MSP430xG461x devices. Two OA modules are implemented in the MSP430FG42x0 devices. Topic Page 22.1 OA Introduction .
Page 640: Oa Introduction
OA Introduction 22.1 OA Introduction The OA op amps support front-end analog signal conditioning prior to analog- to-digital conversion. Features of the OA include: Single supply, low-current operation Rail-to-rail output Software selectable rail-to-rail input Programmable settling time vs power consumption Software selectable configurations Software selectable feedback resistor ladder for PGA implementations Note: Multiple OA Modules...
Page 641 OA Introduction Figure 22−1. OA Block Diagram OAPx=3 OAADC0 OAFCx=6 OANx=3 A12 ext. (OA0) A12 int. (OA0) A13 ext. (OA1) A13 int. (OA1) A14 ext. (OA2) A14 int. (OA2) OAPx OAADC1 OAPMx OAxI0 OAFCx=0 OA0I1 (FG43x) OAxI1 (FG461x) Int. DAC12_0OUT A1 int./ext., OA0O (OA0) OAxOUT Int.
Page 642: Oa Operation
OA Operation 22.2 OA Operation The OA module is configured with user software. The setup and operation of the OA is discussed in the following sections. 22.2.1 OA Amplifier The OA is a configurable, low-current, rail-to-rail operational amplifier. It can be configured as an inverting amplifier, or a non-inverting amplifier, or can be combined with other OA modules to form differential amplifiers.
Page 643: Oa Configurations
OA Operation 22.2.4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits. as listed in Table 22−1. Table 22−1.OA Mode Select OAFCx OA Mode General-purpose op amp Unity gain buffer Reserved Comparator Non-inverting PGA amplifier Reserved Inverting PGA amplifier Differential amplifier...
Page 644 OA Operation Non-Inverting PGA Mode In this mode the output of the OAx is connected to R and R BOTTOM connected to AV . The OAxTAP signal is connected to the inverting input of the OAx providing a non-inverting amplifier configuration with a programmable gain of [1+OAxTAP ratio].
Page 645 OA Operation Figure 22−2 shows an example of a two-opamp differential amplifier using OA0 and OA1. The control register settings and are shown in Table 22−2. The gain for the amplifier is selected by the OAFBRx bits for OA1 and is shown in Table 22−3.
Page 646 OA Operation Figure 22−3. Two Opamp Differential Amplifier OAx Interconnections OAADC0 A13 ext. A13 int. OAPx OAPMx OAADC1 A3 int./ext., OA1O − OAADC1 OAFBRx OAPx OAPMx OA1R BOTTOM − OA0OUT 22-8...
Page 647 OA Operation Figure 22−4 shows an example of a three-opamp differential amplifier using OA0, OA1 and OA2. The control register settings are shown in Table 22−4. The gain for the amplifier is selected by the OAFBRx bits of OA0 and OA2. The OAFBRx settings for both OA0 and OA2 must be equal.
Page 648 OA Operation Figure 22−5. Three-Opamp Differential Amplifier OAx Interconnections OAPx OAADC0 OAPMx A14 ext. A14 int. OA0OUT OAPMx − OAADC1 A5 int./ext., OA2O OAFBRx − OA0TAP OAADC1 OA0TAP OAFBRx OA0R BOTTOM OAPx OAPMx OA2R BOTTOM − OA1OUT 22-10...
Page 649: Oa Modules In Fg42X0 Devices
OA Modules in FG42x0 Devices 22.3 OA Modules in FG42x0 Devices In FG42x0 devices, two operational amplifiers, a DAC, and a sigma-delta converter are combined into a measurement front end. The DAC12 module and the SD16A_1 module are described in separate chapters. The block diagram of the operational amplifier is shown in Figure 22−6.
Page 650: Oa Amplifier
OA Modules in FG42x0 Devices 22.3.1 OA Amplifier Each OA is a configurable low-current operational amplifier with rail-to-rail outputs that can be configured as an inverting amplifier or a non-inverting amplifier. 22.3.2 OA Inputs The OA has configurable input selection. The signals for the + and − inputs are individually selected with the OANx and OAPx bits and can be selected as external signals or internal signals from the DAC12 modules or VSS.
Page 651 OA Modules in FG42x0 Devices Unity Gain Mode In this mode the output of the OAx is connected directly to the inverting input of the OAx providing a unity gain buffer. The non-inverting input is selected by the OAPx bits. The external connection for the inverting input is disabled and the OANx bits are don’t care.
Page 652: Switch Control
OA Modules in FG42x0 Devices Figure 22−8. Transimpedance Amplifier With Two Current Inputs OAPx to SD16_A OA0OUT/A0+ (OA0) DAC12 OA1OUT/A1+ (OA1) − OANx R FB OA0FB/A0− (OA0) OAxI1 OA1FB/A1− (OA1) OAxI2 22.3.5 Switch Control The switch control register SWCTL controls the low resistive switches to ground SW0C and SW1C as well as simplifies the operation of the operational amplifier as transimpedance amplifier.
Page 653: Offset Calibration
OA Modules in FG42x0 Devices 22.3.6 Offset Calibration Figure 22−9 shows the configuration for the offset measurement. To measure the offset of the operational amplifier OAx the unity gain buffer mode needs to be selected with OAFCx = 001 and the positive input of the amplifier needs to be connected to the negative input of the sigma-delta ADC by setting the calibration bit OACAL.
Page 654: Oa Registers
OA Registers 22.4 OA Registers The OA registers are listed in Table 22−8. Table 22−8.OA Registers Register Short Form Register Type Address Initial State OA0 control register 0 OA0CTL0 Read/write 0C0h Reset with PUC OA0 control register 1 OA0CTL1 Read/write 0C1h Reset with PUC OA1 control register 0...
Page 655 OA Registers OAxCTL0, Opamp Control Register 0 OANx OAPx OAPMx OAADC1 OAADC0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 OANx Bits Inverting input select. These bits select the input signal for the OA inverting input. OAxI0 OAxI1 DAC0 internal DAC1 internal OAPx Bits...
Page 656 OA Registers OAxCTL1, Opamp Control Register 1 OAFBRx OAFCx Reserved OARRIP rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 OAFBRx Bits OAx feedback resistor select 000 Tap 0 001 Tap 1 010 Tap 2 011 Tap 3 100 Tap 4 101 Tap 5 110 Tap 6 111 Tap 7...
Page 657: Oa Registers In Fg42X0 Devices
OA Registers in FG42x0 Devices 22.5 OA Registers in FG42x0 Devices The OA registers are listed in Table 22−8. Table 22−9.OA Registers Register Short Form Register Type Address Initial State OA0 control register 0 OA0CTL0 Read/write 0C0h Reset with PUC OA0 control register 1 OA0CTL1 Read/write...
Page 658 OA Registers in FG42x0 Devices OAxCTL0, Opamp Control Register 0 OANx OAPx OAPMx Reserved Reserved rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 OANx Bits Inverting input select 7−6 These bits select the input signal for the OAx inverting input. OAxI1 OAxI2 DAC internal...
Page 659 OA Registers in FG42x0 Devices OAxCTL1, Opamp Control Register 1 Reserved OAFCx OACAL Reserved rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Reserved Bits Reserved 7−5 OAFCx Bit 4−2 OAx function control These bits select the function of OAx 000 General purpose 001 Unity gain buffer 010 Reserved 011 Reserved...
Page 660 OA Registers in FG42x0 Devices SWCTL, Switch Control Register SWCTL7 SWCTL6 SWCTL5 SWCTL4 SWCTL3 SWCTL2 SWCTL1 SWCTL0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 SWCTL7 Bit 7 Shunt switch for OA1 Switch open OA1OUT and OA1FB shorted together SWCTL6 Bit 6 SW1C control Switch open...
Page 661: Comparator_A
Chapter 23 Comparator_A Comparator_A is an analog voltage comparator. This chapter describes Comparator_A. Comparator_A is implemented in all MSP430x4xx devices. Topic Page 23.1 Comparator_A Introduction ........23-2 23.2 Comparator_A Operation .
Page 662: Comparator_A Introduction
Comparator_A Introduction 23.1 Comparator_A Introduction The comparator_A module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals. Features of Comparator_A include: Inverting and non-inverting terminal input multiplexer Software selectable RC-filter for the comparator output Output provided to Timer_A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator...
Page 663 Comparator_A Introduction Figure 23−1. Comparator_A Block Diagram CAEX P2CA0 CAON CCI1B − CAOUT − Set_CAIFG Tau ~ 2.0ms P2CA1 CAREFx CARSEL 0.5x V CAREF 0.25x Comparator_A 23-3...
Page 664: Comparator_A Operation
Comparator_A Operation 23.2 Comparator_A Operation The comparator_A module is configured with user software. The setup and operation of comparator_A is discussed in the following sections. 23.2.1 Comparator The comparator compares the analog voltages at the + and – input terminals. If the + terminal is more positive than the –...
Page 665: Output Filter
Comparator_A Operation 23.2.3 Output Filter The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the input terminals is small.
Page 666: Comparator_A, Port Disable Register Capd
Comparator_A Operation 23.2.5 Comparator_A, Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from V to GND.
Page 667: Comparator_A Used To Measure Resistive Elements
Comparator_A Operation 23.2.7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elements using single slope analog-to-digital conversion. For example, temperature can be converted into digital data using a thermistor, by comparing the thermistor’s capacitor discharge time to that of a reference resistor as shown in Figure 23−5.
Page 668 Comparator_A Operation The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 23−6. Figure 23−6. Timing for Temperature Measurement Systems 0.25 × V meas Phase I: Phase III: Phase IV: Phase II: Charge...
Page 669: Comparator_A Registers
Comparator_A Registers 23.3 Comparator_A Registers The Comparator_A registers are listed in Table 23−1. Table 23−1.Comparator_A Registers Register Short Form Register Type Address Initial State Comparator_A control register 1 CACTL1 Read/write 059h Reset with POR Comparator_A control register 2 CACTL2 Read/write 05Ah Reset with POR Comparator_A port disable...
Page 670 Comparator_A Registers CACTL1, Comparator_A Control Register 1 CAEX CARSEL CAREFx CAON CAIES CAIE CAIFG rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) CAEX Bit 7 Comparator_A exchange. This bit exchanges the comparator inputs and inverts the comparator output. CARSEL Bit 6 Comparator_A reference select.
Page 671 Comparator_A Registers CACTL2, Comparator_A Control Register 2 Unused P2CA1 P2CA0 CAOUT rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) Bits Unused. Unused Bit 3 Pin to CA1. This bit selects the CA1 pin function. P2CA1 The pin is not connected to CA1 The pin is connected to CA1 Bit 2 Pin to CA0.
Page 672 23-12 Comparator_A...
Page 673: Lcd Controller
Chapter 24 LCD Controller The LCD controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes LCD controller. The LCD controller is implemented on all MSP430x4xx devices, except the MSP430x42x0, and MSP430FG461x devices. Topic Page 24.1 LCD Controller Introduction .
Page 674: Lcd Controller Introduction
LCD Controller Introduction 24.1 LCD Controller Introduction The LCD controller directly drives LCD displays by creating the ac segment and common voltage signals automatically. The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs. The LCD controller features are: Display memory Automatic signal generation Configurable frame frequency...
Page 675 LCD Controller Introduction Figure 24−1. LCD Controller Block Diagram SEG39 0A4h SEG38 Segment Display Output Memory Control 8−bits SEG1 SEG0 091h LCDP2 COM3 LCDP1 Common COM2 Output LCDP0 COM1 Control LCDMX1 COM0 LCDMX0 LCDSON LCDON f LCD Analog Timing Generator Voltage (from Basic Timer) Multiplexer...
Page 676: Lcd Controller Operation
LCD Controller Operation 24.2 LCD Controller Operation The LCD controller is configured with user software. The setup and operation of LCD controller is discussed in the following sections. 24.2.1 LCD Memory The LCD memory map is shown in Figure 24−2. Each memory bit corresponds to one LCD segment, or is not used, depending on the mode.
Page 677: Lcd Voltage Generation
LCD Controller Operation 24.2.4 LCD Voltage Generation The voltages required for the LCD signals are supplied externally to pins R33, R23, R13, and R03. Using an equally weighted resistor divider ladder between these pins establishes the analog voltages as shown in Table 24−1. The resistor value R is typically 680 kW.
Page 678: Static Mode
LCD Controller Operation 24.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and one common line, COM0, is used. Figure 24−3 shows some example static waveforms. Figure 24−3. Example Static Waveforms COM0 frame COM0 Resulting Voltage for Segment a (COM0−SP1) Segment Is On.
Page 679 LCD Controller Operation Figure 24−4 shows an example static LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 24−4. Static LCD Example Display Memory Pinout and Connections Connections...
Page 680 LCD Controller Operation Static Mode Software Example All eight segments of a digit are often located in four display memory bytes with the static display method. 001h 010h 002h 020h 004h 040h 008h 080h The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 681: Mux Mode
LCD Controller Operation 24.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and two common lines, COM0 and COM1, are used. Figure 24−5 shows some example 2-mux waveforms. Figure 24−5. Mux Waveforms Example 2- COM1 COM0 frame COM1...
Page 682 LCD Controller Operation Figure 24−6 shows an example 2-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application completely depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 24−6.
Page 683 LCD Controller Operation 2-Mux Mode Software Example All eight segments of a digit are often located in two display memory bytes with the 2mux display rate 002h 020h 008h 004h 040h 001h 080h 010h The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 684: Mux Mode
LCD Controller Operation 24.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments and three common lines, COM0, COM1 and COM2 are used. Figure 24−7 shows some example 3-mux waveforms. Figure 24−7. Mux Waveforms Example 3- COM2 COM0 frame...
Page 685 LCD Controller Operation Figure 24−8 shows an example 3-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 24−8. 3-Mux LCD Example DIGIT10 DIGIT1 Pinout and Connections...
Page 686 LCD Controller Operation 3-Mux Mode Software Example The 3mux rate can support nine segments for each digit. The nine segments of a digit are located in 1 1/2 display memory bytes. 0040h 0400h 0200h 0010h 0001h 0002h 0020h 0100h 0004h LSDigit of register Rx should be displayed.
Page 687: Mux Mode
LCD Controller Operation 24.2.9 4-Mux Mode In 4-mux mode, each MSP430 segment pin drives four LCD segments and all four common lines, COM0, COM1, COM2, and COM3 are used. Figure 24−9 shows some example 4-mux waveforms. Figure 24−9. Mux Waveforms Example 4- COM3 COM0...
Page 688 LCD Controller Operation Figure 24−10 shows an example 4-mux LCD, pin-out, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pin-out and on the MSP430-to-LCD connections. Figure 24−10. 4-Mux LCD Example DIGIT15 DIGIT1 Display Memory...
Page 689 LCD Controller Operation 4-Mux Mode Software Example The 4mux rate supports eight segments for each digit. All eight segments of a digit can often be located in one display memory byte 080h 040h 020h 001h 002h 008h 004h 010h LSDigit of register Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 690: Lcd Controller Registers
LCD Controller Operation 24.3 LCD Controller Registers The LCD Controller registers are listed in Table 24−2. Table 24−2.LCD Controller Registers Register Short Form Register Type Address Initial State LCD control register LCDCTL Read/write 090h Reset with PUC LCD memory 1 LCDM1 Read/write 091h...
Page 691 LCD Controller Operation LCDCTL, LCD Control Register LCDPx LCDMXx LCDSON Unused LCDON rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 LCDPx Bits LCD Port Select. These bits select the pin function to be port I/O or LCD function for groups of segments pins. These bits ONLY affect pins with multiplexed functions.
Page 692 24-20 LCD Controller...
Page 693: Lcd_A Controller
Chapter 25 LCD_A Controller The LCD_A controller drives static, 2-mux, 3-mux, or 4-mux LCDs. This chapter describes the LCD_A controller. The LCD_A controller is implemented on the MSP430x42x0 and MSP430FG46xx devices. Topic Page 25.1 LCD Controller Introduction ........25-2 25.2 LCD Controller Operation .
Page 694: Lcd_A Controller Introduction
LCD_A Controller Introduction 25.1 LCD_A Controller Introduction The LCD_A controller directly drives LCD displays by creating the ac segment and common voltage signals automatically. The MSP430 LCD controller can support static, 2-mux, 3-mux, and 4-mux LCDs. The LCD controller features are: Display memory Automatic signal generation Configurable frame frequency...
Page 695 LCD_A Controller Introduction Figure 25−1. LCD_A Controller Block Diagram SEG39 0A4h SEG38 Segment Display Output Memory Control 8−bits SEG1 SEG0 091h COM3 LCDSx Common COM2 LCDSON Output COM1 Control COM0 V LCD LCDON LCDFREQx Analog Voltage f LCD Timing Divider ACLK Multiplexer Generator...
Page 696: Lcd_A Controller Operation
LCD_A Controller Operation 25.2 LCD_A Controller Operation The LCD_A controller is configured with user software. The setup and operation of the LCD_A controller is discussed in the following sections. 25.2.1 LCD Memory The LCD memory map is shown in Figure 25−2. Each memory bit corresponds to one LCD segment, or is not used, depending on the mode.
Page 697: Lcd_A Voltage And Bias Generation
LCD_A Controller Operation 25.2.3 LCD_A Voltage And Bias Generation The LCD_A module allows selectable sources for the peak output waveform voltage, V1 as well as the fractional LCD biasing voltages V2 − V5. V be sourced from AV , an internal charge pump, or externally. All internal voltage generation is disabled if the oscillator sourcing ACLK is turned off (OSCOFF = 1) or the LCD_A module is disabled (LCDON = 0).
Page 698 LCD_A Controller Operation To source the bias voltages V2 − V4 externally, REXT is set. This also disables the internal bias generation. Typically an equally weighted resistor divider is used with resistors ranging from 100 kW to 1 MW. When using an external resistor divider, the V voltage may be sourced from the internal charge pump when VLCDEXT = 0.
Page 699 LCD_A Controller Operation The internal bias generator supports 1/2 bias LCDs when LCD2B = 1, and 1/3 bias LCDs when LCD2B = 0 in 2-mux, 3-mux, and 4-mux modes. In static mode, the internal divider is disabled. Some devices share the LCDCAP, R33, and R23 functions. In this case, the charge pump cannot be used together with an external resistor divider with 1/3 biasing.
Page 700: Lcd Timing Generation
LCD_A Controller Operation 25.2.4 LCD Timing Generation The LCD_A controller uses the f signal from the integrated ACLK prescaler to generate the timing for common and segment lines. ACLK is assumed to be 32768 Hz for generating f . The f frequency is selected with the LCDFREQx bits.
Page 701: Static Mode
LCD_A Controller Operation 25.2.6 Static Mode In static mode, each MSP430 segment pin drives one LCD segment and one common line, COM0, is used. Figure 25−4 shows some example static waveforms. Figure 25−4. Example Static Waveforms COM0 frame COM0 Resulting Voltage for Segment a (COM0−SP1) Segment Is On.
Page 702 LCD_A Controller Operation Figure 25−5 shows an example static LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 25−5. Static LCD Example DIGIT4 DIGIT1 Display Memory...
Page 703 LCD_A Controller Operation Static Mode Software Example All eight segments of a digit are often located in four display memory bytes with the static display method. 001h 010h 002h 020h 004h 040h 008h 080h The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 704: Mux Mode
LCD_A Controller Operation 25.2.7 2-Mux Mode In 2-mux mode, each MSP430 segment pin drives two LCD segments and two common lines, COM0 and COM1, are used. Figure 25−6 shows some example 2-mux, 1/2 bias waveforms. Figure 25−6. Mux Waveforms Example 2- COM1 COM0 frame...
Page 705 LCD_A Controller Operation Figure 25−7 shows an example 2-mux LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application completely depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 25−7.
Page 706 LCD_A Controller Operation 2-Mux Mode Software Example All eight segments of a digit are often located in two display memory bytes with the 2mux display rate 002h 020h 008h 004h 040h 001h 080h 010h The register content of Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 707: Mux Mode
LCD_A Controller Operation 25.2.8 3-Mux Mode In 3-mux mode, each MSP430 segment pin drives three LCD segments and three common lines (COM0, COM1, and COM2) are used. Figure 25−8 shows some example 3-mux, 1/3 bias waveforms. Figure 25−8. Mux Waveforms Example 3- COM2 COM0...
Page 708 LCD_A Controller Operation Figure 25−9 shows an example 3-mux LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 25−9. 3-Mux LCD Example DIGIT10 DIGIT1 Pinout and Connections...
Page 709 LCD_A Controller Operation 3-Mux Mode Software Example The 3mux rate can support nine segments for each digit. The nine segments of a digit are located in 1 1/2 display memory bytes. 0040h 0400h 0200h 0010h 0001h 0002h 0020h 0100h 0004h LSDigit of register Rx should be displayed.
Page 710: Mux Mode
LCD_A Controller Operation 25.2.9 4-Mux Mode In 4-mux mode, each MSP430 segment pin drives four LCD segments and all four common lines (COM0, COM1, COM2, and COM3) are used. Figure 25−10 shows some example 4-mux, 1/3 bias waveforms. Figure 25−10. Mux Waveforms Example 4- COM3...
Page 711 LCD_A Controller Operation Figure 25−11 shows an example 4-mux LCD, pinout, LCD-to-MSP430 connections, and the resulting segment mapping. This is only an example. Segment mapping in a user’s application depends on the LCD pinout and on the MSP430-to-LCD connections. Figure 25−11.4-Mux LCD Example DIGIT15 DIGIT1 Display Memory...
Page 712 LCD_A Controller Operation 4-Mux Mode Software Example The 4mux rate supports eight segments for each digit. All eight segments of a digit can often be located in one display memory byte 080h 040h 020h 001h 002h 008h 004h 010h LSDigit of register Rx should be displayed. The Table represents the ’on’−segments according to the content of Rx.
Page 713: Lcd Controller Registers
LCD_A Controller Operation 25.3 LCD Controller Registers The LCD Controller registers are listed in Table 25−2. Table 25−2.LCD Controller Registers Register Short Form Register Type Address Initial State LCD_A control register LCDACTL Read/write 090h Reset with PUC LCD memory 1 LCDM1 Read/write 091h...
Page 714 LCD_A Controller Operation LCDACTL, LCD_A Control Register LCDFREQx LCDMXx LCDSON Unused LCDON rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 LCDFREQx Bits LCD Frequency Select. These bits select the ACLK divider for the LCD frequency. 000 Divide by 32 001 Divide by 64 010 Divide by 96 011 Divide by 128 100 Divide by 192...
Page 715 LCD_A Controller Operation LCDAPCTL0, LCD_A Port Control Register 0 LCDS28 LCDS24 LCDS20 LCDS16 LCDS12 LCDS8 LCDS4 LCDS0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 LCDS28 Bit 7 LCD Segment 28 to 31 Enable. This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function.
Page 716 LCD_A Controller Operation LCDAPCTL1, LCD_A Port Control Register 1 Unused LCDS36 LCDS32 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Unused Bits Unused 7−2 LCDS36 Bit 1 LCD Segment 36 to 39 Enable. This bit only affects pins with multiplexed functions. Dedicated LCD pins are always LCD function.
Page 717 LCD_A Controller Operation LCDAVCTL0, LCD_A Voltage Control Register 0 Unused R03EXT REXT VLCDEXT LCDCPEN VLCDREFx LCD2B rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Unused Bit 7 Unused R03EXT Bit 6 V5 voltage select. This bit selects the external connection for the lowest LCD voltage.
Page 718 LCD_A Controller Operation LCDAVCTL1, LCD_A Voltage Control Register 1 Unused VLCDx Unused rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Unused Bits Unused 7−5 VLCDx Bits Charge pump voltage select. LCDCPEN must be 1 for the charge pump to 4−1 be enabled.
Page 719: Adc12
Chapter 26 ADC12 The ADC12 module is a high-performance 12-bit analog-to-digital converter (ADC). This chapter describes the ADC12. The ADC12 is implemented in the MSP430x43x MSP430x44x, and MSP430FG461x devices. Topic Page 26.1 ADC12 Introduction ......... . 26-2 26.2 ADC12 Operation .
Page 720: Adc12 Introduction
ADC12 Introduction 26.1 ADC12 Introduction The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator word conversion-and-control buffer. conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. ADC12 features include: Greater than 200-ksps maximum conversion rate Monotonic 12-bit converter with no missing codes...
Page 721 ADC12 Introduction Figure 26−1. ADC12 Block Diagram REFON REF2_5V INCHx=0Ah Ve REF+ V REF+ 1.5 V or 2.5 V V REF− / Ve REF− Reference Ref_x INCHx SREF1 SREF0 ADC12OSC ADC12SSELx 0000 SREF2 ADC12ON 0001 0001 ADC12DIVx 0010 0011 V R− V R+ Sample 0100...
Page 722: Adc12 Operation
ADC12 Operation 26.2 ADC12 Operation The ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed in the following sections. 26.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation and stores result conversion...
Page 723: Adc12 Inputs And Multiplexer
ADC12 Operation 26.2.2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection resulting from channel switching as shown in Figure 26−2.
Page 724: Voltage Reference Generator
ADC12 Operation 26.2.3 Voltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectable voltage levels, 1.5 V and 2.5 V. Either of these reference voltages may be used internally and externally on pin V REF+ Setting REFON=1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V, the reference is 1.5 V when REF2_5V = 0.
Page 725: Sample And Conversion Timing
ADC12 Operation 26.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following: The ADC12SC bit The Timer_A Output Unit 1 The Timer_B Output Unit 0 The Timer_B Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit.
Page 726 ADC12 Operation Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used to trigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period The sampling timer keeps SAMPCON high after synchronization with sample.
Page 727 ADC12 Operation Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time t , as shown below in Figure 26−5. An internal MUX-on sample input resistance R (maximum 2 kΩ) in series with capacitor C...
Page 728: Conversion Memory
ADC12 Operation 26.2.6 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversion results. Each ADC12MEMx is configured with an associated ADC12MCTLx control register. The SREFx bits define the voltage reference and the INCHx bits select the input channel. The EOS bit defines the end of sequence when a sequential conversion mode is used.
Page 729 ADC12 Operation Single-Channel Single-Conversion Mode A single channel is sampled and converted once. The ADC result is written to the ADC12MEMx defined by the CSTARTADDx bits. Figure 26−6 shows the flow of the Single-Channel, Single-Conversion mode. When ADC12SC triggers a conversion, successive conversions can be triggered by the ADC12SC bit.
Page 730 ADC12 Operation Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The ADC results are written to the conversion memories starting with the ADCMEMx defined by the CSTARTADDx bits. The sequence stops after the measurement of the channel with a set EOS bit. Figure 26−7 shows the sequence-of-channels mode.
Page 731 ADC12 Operation Repeat-Single-Channel Mode A single channel is sampled and converted continuously. The ADC results are written to the ADC12MEMx defined by the CSTARTADDx bits. It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion. Figure 26−8 shows repeat-single-channel mode Figure 26−8.
Page 732 ADC12 Operation Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDx bits. The sequence ends after the measurement of the channel with a set EOS bit and the next trigger signal re-starts the sequence.
Page 733 ADC12 Operation Using the Multiple Sample and Convert (MSC) Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1, CONSEQx > 0, and the sample timer is used, the first rising edge of the SHI signal triggers the first conversion.
Page 734: Using The Integrated Temperature Sensor
ADC12 Operation 26.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc.
Page 735: Adc12 Grounding And Noise Considerations
ADC12 Operation 26.2.9 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry.
Page 736: Adc12 Interrupts
ADC12 Operation 26.2.10 ADC12 Interrupts The ADC12 has 18 interrupt sources: ADC12IFG0-ADC12IFG15 ADC12OV, ADC12MEMx overflow ADC12TOV, ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result. An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set.
Page 737 ADC12 Operation ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead. The ADC12IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 738: Adc12 Registers
ADC12 Registers 26.3 ADC12 Registers The ADC12 registers are listed in Table 26−2 . Table 26−2.ADC12 Registers Register Short Form Register Type Address Initial State ADC12 control register 0 ADC12CTL0 Read/write 01A0h Reset with POR ADC12 control register 1 ADC12CTL1 Read/write 01A2h Reset with POR...
Page 739 ADC12 Registers ADC12CTL0, ADC12 Control Register 0 SHT1x SHT0x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) ADC12 REF2_5V REFON ADC12ON ADC12OVIE ADC12SC TOVIE rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 SHT1x Bits Sample-and-hold time.
Page 740 ADC12 Registers Bit 7 Multiple sample and conversion. Valid only for sequence or repeated modes. The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversions are performed automatically as soon as the prior conversion is completed.
Page 741 ADC12 Registers ADC12CTL1, ADC12 Control Register 1 CSTARTADDx SHSx ISSH rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) ADC12 ADC12DIVx ADC12SSELx CONSEQx BUSY rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) r−(0) Modifiable only when ENC = 0 CSTART Bits Conversion start address.
Page 742 ADC12 Registers ADC12 Bits ADC12 clock source select SSELx ADC12OSC ACLK MCLK SMCLK CONSEQx Bits Conversion sequence mode select Single-channel, single-conversion Sequence-of-channels Repeat-single-channel Repeat-sequence-of-channels ADC12 Bit 0 ADC12 busy. This bit indicates an active sample or conversion operation. BUSY No operation is active. A sequence, sample, or conversion is active.
Page 743 ADC12 Registers ADC12MCTLx, ADC12 Conversion Memory Control Registers SREFx INCHx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Modifiable only when ENC = 0 Bit 7 End of sequence. Indicates the last conversion in a sequence. Not end of sequence End of sequence SREFx Bits...
Page 744 ADC12 Registers ADC12IE, ADC12 Interrupt Enable Register ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IE9 ADC12IE8 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) ADC12IE7 ADC12IE6 ADC12IE5 ADC12IE4 ADC12IE3 ADC12IE2 ADC12IE1 ADC12IE0 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) ADC12IEx Bits Interrupt enable.
Page 745 ADC12 Registers ADC12IV, ADC12 Interrupt Vector Register ADC12IVx r−(0) r−(0) r−(0) r−(0) r−(0) ADC12IVx Bits ADC12 interrupt vector value 15-0 ADC12IV Interrupt Contents Priority Interrupt Source Interrupt Flag 000h No interrupt pending − 002h ADC12MEMx overflow − Highest 004h Conversion time overflow −...
Page 746 26-28 ADC12...
Page 747 Chapter 27 SD16 The SD16 module is a multichannel 16-bit, sigma-delta analog-to-digital converter. This chapter describes the SD16. The SD16 module is implemented in the MSP430FE42x and MSP430F42x devices. Topic Page 27.1 SD16 Introduction ......... . . 27-2 27.2 SD16 Operation .
Page 748: Sd16 Introduction
SD16 Introduction 27.1 SD16 Introduction The SD16 module consists of up to three independent sigma-delta analog-to-digital converters and an internal voltage reference. Each channel has up to 8 fully differential multiplexed analog input pairs including a built-in temperature sensor. The converters are based on second-order oversampling sigma-delta modulators and digital decimation filters.
Page 749 SD16 Introduction Figure 27−1. SD16 Block Diagram SD16 Control Block SD16REFON SD16SSELx Reference V REF AV CC 1.2V SD16DIVx Reference MCLK AV SS SMCLK Divider 1/2/4/8 ACLK TACLK SD16VMIDON Temperature sensor Reference Channel 0 Channel 1 Conversion Control Reference (to prior channel) Temperature sensor SD16GRP Group/Start...
Page 750: Sd16 Operation
SD16 Operation 27.2 SD16 Operation The SD16 module is configured with user software. The setup and operation of the SD16 is discussed in the following sections. 27.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency f .
Page 751: Analog Input Pair Selection
SD16 Operation 27.2.5 Analog Input Pair Selection Each SD16 channel can convert up to 8 differential input pairs multiplexed into the PGA. Up to six input pairs (A0-A5) are available externally on the device. See the device-specific data sheet for analog input pin information. An internal temperature sensor is available to each channel using the A6 multiplexer input.
Page 752: Analog Input Characteristics
SD16 Operation 27.2.6 Analog Input Characteristics The SD16 uses a switched-capacitor input stage that appears as an impedance to external circuitry as shown in Figure 27−2. Figure 27−2. Analog Input Equivalent Circuit MSP430 = Positive external source voltage = Negative external source voltage S−...
Page 753: Digital Filter
SD16 Operation 27.2.7 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC comb filter. The transfer function is described in the z-Domain by: 1 * z *OSR H ( z ) + 1 * z and in the frequency domain by: sinc OSRp sin OSR...
Page 754 SD16 Operation Figure 27−4 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input.
Page 755 SD16 Operation Digital Filter Output The number of bits output by each digital filter is dependent on the oversampling ratio and ranges from 16 to 24 bits. Figure 27−5 shows the digital filter output bits and their relation to SD16MEMx for each OSR. For example, for OSR = 256 and LSBACC = 0, the SD16MEMx register contains bits 23 −...
Page 756: Conversion Memory Registers: Sd16Memx
SD16 Operation 27.2.8 Conversion Memory Registers: SD16MEMx One SD16MEMx register is associated with each SD16 channel. Conversion results for each channel are moved to the corresponding SD16MEMx register with each decimation step of the digital filter. The SD16IFG bit for a given channel is set when new data is written to SD16MEMx.
Page 757: Conversion Modes
SD16 Operation 27.2.9 Conversion Modes The SD16 module can be configured for four modes of operation, listed in Table 27−3. The SD16SNGL and SD16GRP bits for each channel selects the conversion mode. Table 27−3.Conversion Mode Summary SD16SNGL SD16GRP{ Mode Operation Single channel, A single channel is Single conversion...
Page 758 SD16 Operation Figure 27−7. Single Channel Operation − Example Conversion Channel 0 SD16SNGL = 1 SD16GRP = 0 Auto−clear SD16SC Set by SW Conversion Conversion Channel 1 SD16SNGL = 1 SD16GRP = 0 Auto−clear Auto−clear Set by SW Set by SW SD16SC Conversion Conversion...
Page 759 SD16 Operation Group of Channels, Continuous Conversion When SD16SNGL = 0 for a channel in a group, continuous conversion mode is selected. Continuous conversion of that channel will occur synchronously when the master channel SD16SC bit is set. SD16SC bits for all grouped channels will be automatically set and cleared with the master channel’s SD16SC bit.
Page 760: Conversion Operation Using Preload
SD16 Operation 27.2.10 Conversion Operation Using Preload When multiple channels are grouped the SD16PREx registers can be used to delay the conversion time frame for each channel. Using SD16PREx, the decimation time of the digital filter is increased by the specified number of f clock cycles and can range from 0 to 255.
Page 761 SD16 Operation Figure 27−10. Start of Conversion using Preload − Example SD16OSRx = 32 f M cycles: SD16PRE0 = 8 Delayed Conversion Conversion Conversion 1 st Sample Ch0 SD16PRE1 = 0 Conversion Conversion Conversion Conversion 1 st Sample Ch1 Start of Time Conversion When channels are grouped, care must be taken when a channel or channels...
Page 762: Using The Integrated Temperature Sensor
SD16 Operation 27.2.11 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input pair SD16INCHx = 110 and sets SD16REFON = 1. Any other configuration is done as if an external analog input pair was selected, including SD16INTDLYx and SD16GAINx settings.
Page 763: Interrupt Handling
SD16 Operation 27.2.12 Interrupt Handling The SD16 has 2 interrupt sources for each ADC channel: SD16IFG SD16OVIFG The SD16IFG bits are set when their corresponding SD16MEMx memory register is written with a conversion result. An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set. The SD16 overflow condition occurs when a conversion result is written to any SD16MEMx location before the previous conversion result was read.
Page 764 SD16 Operation SD16 Interrupt Handling Software Example The following software example shows the recommended use of SD16IV and the handling overhead. The SD16IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 765: Sd16 Registers
SD16 Registers 27.3 SD16 Registers The SD16 registers are listed in Table 27−4: Table 27−4.SD16 Registers Register Short Form Register Type Address Initial State SD16 Control SD16CTL Read/write 0100h Reset with PUC SD16 Interrupt Vector SD16IV Read/write 0110h Reset with PUC SD16 Channel 0 Control SD16CCTL0 Read/write...
Page 766 SD16 Registers SD16CTL, SD16 Control Register Reserved SD16LP rw−0 SD16 SD16 SD16DIVx SD16SSELx SD16OVIE Reserved VMIDON REFON rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Reserved Bits Reserved 15-9 SD16LP Bit 8 Low power mode. This bit selects a reduced speed, reduced power mode for the SD16.
Page 767 SD16 Registers SD16CCTLx, SD16 Channel x Control Register Reserved SD16SNGL SD16OSRx rw−0 rw−0 rw−0 SD16 SD16 SD16 SD16DF SD16IE SD16IFG SD16SC SD16GRP LSBTOG LSBACC OVIFG rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 r(w)−0 Reserved Bits Reserved 15-11 SD16SNGL Bit 10 Single conversion mode select Continuous conversion mode Single conversion mode...
Page 768 SD16 Registers SD16IFG Bit 2 SD16 interrupt flag. SD16IFG is set when new conversion results are available. SD16IFG is automatically reset when the corresponding SD16MEMx register is read, or may be cleared with software. No interrupt pending Interrupt pending SD16SC Bit 1 SD16 start conversion No conversion start...
Page 769 SD16 Registers SD16MEMx, SD16 Channel x Conversion Memory Register Conversion Results Conversion Results Conversion Bits Conversion Results. The SD16MEMx register holds the upper or lower Result 15-0 16-bits of the digital filter output, depending on the SD16LSBACC bit. SD16PREx, SD16 Channel x Preload Register Preload Value rw−0 rw−0...
Page 770 SD16 Registers SD16IV, SD16 Interrupt Vector Register SD16IVx r−0 r−0 r−0 r−0 SD16IVx Bits SD16 interrupt vector value 15-0 SD16IV Interrupt Contents Priority Interrupt Source Interrupt Flag 000h No interrupt pending − 002h SD16MEMx overflow SD16CCTLx Highest † SD16OVIFG 004h SD16_0 Interrupt SD16CCTL0 SD16IFG...
Page 771: Sd16_A
Chapter 28 SD16_A The SD16_A module is a multichannel 16-bit, sigma-delta analog-to-digital converter (ADC). This chapter describes the SD16_A. The SD16_A module is implemented in the MSP430F42x0, MSP430FG42x0, and MSP430F47x devices. Topic Page 28.1 SD16_A Introduction ......... 28-2 28.2 SD16_A Operation .
Page 772: Sd16_A Introduction
SD16_A Introduction 28.1 SD16_A Introduction The SD16_A module consists of up to seven independent sigma-delta analog-to-digital converters, referred to as channels, and an internal voltage reference. Each channel has up to eight fully differential multiplexed analog input pairs including a built-in temperature sensor and a divided supply voltage.
Page 773 SD16_A Introduction Figure 28−1. MSP430F47x SD16_A Block Diagram SD16_A Control Block SD16REFON SD16SSELx Reference V REF AV CC 1.2V SD16XDIVx SD16DIVx MCLK AV SS SMCLK Divider Divider 1/2/4/8 1/3/16/48 Reference ACLK TACLK SD16VMIDON Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Ì Channel 0 Ì...
Page 774 SD16_A Introduction Figure 28−2. MSP430F42x0 and MSP430FG42x0 SD16_A Block Diagram SD16REFON SD16SSELx Reference V REF AV CC 1.2V SD16DIVx SD16XDIVx MCLK AV SS SMCLK Divider Divider 1/2/4/8 1/3/16/48 Reference ACLK TACLK SD16VMIDON Start Conversion SD16SC SD16INCHx Logic SD16SNGL − SD16BUFx SD16OSRx −...
Page 775: Sd16_A Operation
SD16_A Operation 28.2 SD16_A Operation The SD16_A module is configured with user software. The setup and operation of the SD16_A is discussed in the following sections. 28.2.1 ADC Core The analog-to-digital conversion is performed by a 1-bit, second-order sigma-delta modulator. A single-bit comparator within the modulator quantizes the input signal with the modulator frequency f .
Page 776: Analog Input Pair Selection
SD16_A Operation 28.2.5 Analog Input Pair Selection The SD16_A can convert up to 8 differential input pairs multiplexed into the PGA. Up to five analog input pairs (A0-A4) are available externally on the device. A resistive divider to measure the supply voltage is available using the A5 multiplexer input.
Page 777: Analog Input Characteristics
SD16_A Operation 28.2.6 Analog Input Characteristics The SD16_A uses a switched-capacitor input stage that appears as an impedance to external circuitry as shown in Figure 28−3. Figure 28−3. Analog Input Equivalent Circuit MSP430 = Positive external source voltage = Negative external source voltage S−...
Page 778: Digital Filter
SD16_A Operation 28.2.7 Digital Filter The digital filter processes the 1-bit data stream from the modulator using a SINC comb filter. The transfer function is described in the z-Domain by: 1 * z *OSR H ( z ) + 1 * z and in the frequency domain by: sinc OSRp sin OSR...
Page 779 SD16_A Operation Figure 28−5 shows the digital filter step response and conversion points. For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available. The SD16INTDLYx bits can provide sufficient filter settling time for a full-scale change at the ADC input.
Page 780 SD16_A Operation Digital Filter Output The number of bits output by the digital filter is dependent on the oversampling ratio and ranges from 15 to 30 bits. Figure 28−6 shows the digital filter output and their relation to SD16MEMx for each OSR, LSBACC, and SD16UNI setting.
Page 781 SD16_A Operation OSR=256, LSBACC=0, SD16UNI=1 28 27 26 25 23 22 21 19 18 17 15 14 13 11 10 OSR=256, LSBACC=1, SD16UNI=1 28 27 26 25 23 22 21 19 18 17 15 14 13 11 10 OSR=256, LSBACC=0, SD16UNI=0 28 27 26 25 23 22 21 19 18 17...
Page 782: Conversion Memory Register: Sd16Memx
SD16_A Operation 28.2.8 Conversion Memory Register: SD16MEMx One SD16MEMx register is associated with each SD16_A channel. Conversion results are moved to the corresponding SD16MEMx register with each decimation step of the digital filter. The SD16IFG bit is set when new data is written to SD16MEMx.
Page 783 SD16_A Operation Figure 28−7 shows the relationship between the full-scale input voltage range from −V to +V and the conversion result. The data formats are illustrated. Figure 28−7. Input Voltage vs. Digital Output Bipolar Output: Offset Binary Bipolar Output: 2’s complement Unipolar Output SD16MEMx SD16MEMx...
Page 784: Conversion Modes
SD16_A Operation 28.2.9 Conversion Modes The SD16_A module can be configured for four modes of operation, listed in Table 28−4. The SD16SNGL and SD16GRP bits for each channel selects the conversion mode. Table 28−4.Conversion Mode Summary † SD16SNGL SD16GRP Mode Operation Single channel, A single channel is...
Page 785 SD16_A Operation Figure 28−8. Single Channel Operation − Example Conversion Channel 0 SD16SNGL = 1 SD16GRP = 0 Auto−clear SD16SC Set by SW Conversion Conversion Channel 1 SD16SNGL = 1 SD16GRP = 0 Auto−clear Auto−clear Set by SW Set by SW SD16SC Conversion Conversion...
Page 786 SD16_A Operation Group of Channels, Continuous Conversion When SD16SNGL = 0 for a channel in a group, continuous conversion mode is selected. Continuous conversion of that channel will occur synchronously when the master channel SD16SC bit is set. SD16SC bits for all grouped channels will be automatically set and cleared with the master channel’s SD16SC bit.
Page 787: Conversion Operation Using Preload
SD16_A Operation 28.2.10 Conversion Operation Using Preload When multiple channels are grouped the SD16PREx registers can be used to delay the conversion time frame for each channel. Using SD16PREx, the decimation time of the digital filter is increased by the specified number of f clock cycles and can range from 0 to 255.
Page 788 SD16_A Operation Figure 28−11.Start of Conversion using Preload − Example SD16OSRx = 32 f M cycles: SD16PRE0 = 8 Delayed Conversion Conversion Conversion 1 st Sample Ch0 SD16PRE1 = 0 Conversion Conversion Conversion Conversion 1 st Sample Ch1 Start of Time Conversion When channels are grouped, care must be taken when a channel or channels...
Page 789: Using The Integrated Temperature Sensor
SD16_A Operation 28.2.11 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, the user selects the analog input pair SD16INCHx = 110 and sets SD16REFON = 1. Any other configuration is done as if an external analog input pair was selected, including SD16INTDLYx and SD16GAINx settings.
Page 790: Interrupt Handling
SD16_A Operation 28.2.12 Interrupt Handling The SD16_A has 2 interrupt sources for each ADC channel: SD16IFG SD16OVIFG The SD16IFG bits are set when their corresponding SD16MEMx memory register is written with a conversion result. An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set. The SD16_A overflow condition occurs when a conversion result is written to any SD16MEMx location before the previous conversion result was read.
Page 791 SD16_A Operation SD16_A Interrupt Handling Software Example The following software example shows the recommended use of SD16IV and the handling overhead. The SD16IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction.
Page 792: Sd16_A Registers
SD16_A Registers 28.3 SD16_A Registers The SD16_A registers are listed in Table 28−5 (registers for channels not implemented are unavailable; see the device-specific data sheet): Table 28−5.SD16_A Registers Register Short Form Register Type Address Initial State SD16_A Control SD16CTL Read/write 0100h Reset with PUC SD16_A Interrupt Vector...
Page 793 SD16_A Registers SD16CTL, SD16_A Control Register Reserved SD16XDIVx SD16LP rw−0 rw−0 rw−0 rw−0 SD16 SD16 SD16DIVx SD16SSELx SD16OVIE Reserved REFON VMIDON rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 Reserved Bits Reserved 15-12 SD16XDIVx Bits SD16_A clock divider 11-9 000 /1 001 /3 010 /16 011 /48...
Page 794 SD16_A Registers SD16CCTLx, SD16_A Channel x Control Register † Reserved SD16BUFx SD16UNI SD16XOSR SD16SNGL SD16OSRx rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 SD16 SD16 SD16 ‡ SD16DF SD16IE SD16IFG SD16SC SD16GRP LSBTOG LSBACC OVIFG rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 rw−0 r(w)−0 †...
Page 795 SD16_A Registers SD16 Bit 6 LSB access. This bit allows access to the upper or lower 16-bits of the LSBACC SD16_A conversion result. SD16MEMx contains the most significant 16-bits of the conversion. SD16MEMx contains the least significant 16-bits of the conversion. SD16OVIFG Bit 5 SD16_A overflow interrupt flag...
Page 796 SD16_A Registers SD16GAINx Bits SD16_A preamplifier gain 000 x1 001 x2 010 x4 011 x8 100 x16 101 x32 110 Reserved 111 Reserved SD16INCHx Bits SD16_A channel differential pair input. The available selections are device dependent. See the device-specific data sheet. 000 Ax.0 −...
Page 797 SD16_A Registers SD16MEMx, SD16_A Channel x Conversion Memory Register Conversion Results Conversion Results Conversion Bits Conversion Results. The SD16MEMx register holds the upper or lower Result 15-0 16-bits of the digital filter output, depending on the SD16LSBACC bit. SD16PREx, SD16_A Channel x Preload Register (Not present on MSP430F42x0 and MSP430FG42x0) Preload Value rw−0...
Page 798 SD16_A Registers SD16AEx Bits SD16_A analog enable External input disabled. Negative inputs are internally connected to VSS. External input enabled. SD16IV, SD16_A Interrupt Vector Register SD16IVx r−0 r−0 r−0 r−0 SD16IVx Bits SD16_A interrupt vector value 15-0 SD16IV Interrupt Contents Priority Interrupt Source Interrupt Flag...
Page 799: Dac12
Chapter 29 DAC12 The DAC12 module is a 12-bit, voltage output digital-to-analog converter. This chapter describes the DAC12. Two DAC12 modules are implemented in the MSP430FG43x and MSP430FG461x devices. Only DAC12_0 is implemented in MSP430x42x0 devices. Topic Page 29.1 DAC12 Introduction .
Page 800: Dac12 Introduction
DAC12 Introduction 29.1 DAC12 Introduction The DAC12 module is a 12-bit, voltage output DAC. The DAC12 can be configured in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous update operation.
Page 801 DAC12 Introduction Figure 29−1. DAC12 Block Diagram Ve REF+ To ADC12 module V REF+ 2.5V or 1.5V reference from ADC12 DAC12SREFx DAC12AMPx DAC12IR AV SS V R− V R+ DAC12LSELx DAC12_0OUT DAC12_0 Latch Bypass DAC12RES DAC12_0Latch DAC12DF DAC12GRP DAC12ENC DAC12_0DAT DAC12_0DAT Updated Group Load...
Page 802 DAC12 Introduction Figure 29−2. DAC12 Block Diagram For MSPx42x0 Devices V REF 1.2V reference from SD16 DAC12SREFx DAC12AMPx DAC12IR DAC12IR AV CC AV SS V R− V R+ DAC12LSELx DAC12_0OUT DAC12_0 Latch Bypass DAC12RES DAC12_0Latch DAC12DF DAC12GRP DAC12_0DAT DAC12_0DAT Updated 29-4 DAC12...
Page 803: Dac12 Operation
DAC12 Operation 29.2 DAC12 Operation The DAC12 module is configured with user software. The setup and operation of the DAC12 is discussed in the following sections. 29.2.1 DAC12 Core The DAC12 can be configured to operate in 8-bit or 12-bit mode using the DAC12RES bit.
Page 804: Dac12 Reference
DAC12 Operation 29.2.2 DAC12 Reference On MSP430FG43x and MSP430FG461x devices, the reference for the DAC12 is configured to use either an external reference voltage or the internal 1.5-V/2.5-V reference from the ADC12 module with the DAC12SREFx bits. When DAC12SREFx = {0,1} the V signal is used as the reference and REF+ when DAC12SREFx = {2,3} the Ve...
Page 805: Dac12_Xdat Data Format
DAC12 Operation 29.2.4 DAC12_xDAT Data Format The DAC12 supports both straight binary and 2s compliment data formats. When using straight binary data format, the full-scale output value is 0FFFh in 12-bit mode (0FFh in 8-bit mode) as shown in Figure 29−3. Figure 29−3.
Page 806: Dac12 Output Amplifier Offset Calibration
DAC12 Operation 29.2.5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative. When the offset is negative, the output amplifier attempts to drive the voltage negative, but cannot do so. The output voltage remains at zero until the DAC12 digital input produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 29−5.
Page 807: Grouping Multiple Dac12 Modules
DAC12 Operation 29.2.6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output. Hardware ensures that all DAC12 modules in a group update simultaneously independent of any interrupt or NMI event. On the MSP430FG43x and MSP430FG461x devices, DAC12_0 and DAC12_1 are grouped by setting the DAC12GRP bit of DAC12_0.
Page 808: Dac12 Interrupts
DAC12 Operation 29.2.7 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller on some devices (see device-specific datasheet for interrupt assignment). In this case, software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt.
Page 809: Dac12 Registers
DAC12 Registers 29.3 DAC12 Registers The DAC12 registers are listed in Table 29−2. Table 29−2.DAC12 Registers Register Short Form Register Type Address Initial State DAC12_0 control DAC12_0CTL Read/write 01C0h Reset with POR DAC12_0 data DAC12_0DAT Read/write 01C8h Reset with POR DAC12_1 control DAC12_1CTL Read/write...
Page 810 DAC12 Registers DAC12_xCTL, DAC12 Control Register DAC12 DAC12OPS DAC12SREFx DAC12RES DAC12LSELx DAC12IR CALON rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) DAC12 DAC12AMPx DAC12DF DAC12IE DAC12IFG DAC12ENC rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Modifiable only when DAC12ENC = 0 DAC12OPS Bit 15 DAC12 output select...
Page 811 DAC12 Registers DAC12 Bit 9 DAC12 calibration on. This bit initiates the DAC12 offset calibration sequence CALON and is automatically reset when the calibration completes. Calibration is not active Initiate calibration/calibration in progress DAC12IR Bit 8 DAC12 input range. This bit sets the reference input and voltage output range. DAC12 full-scale output = 3x reference voltage DAC12 full-scale output = 1x reference voltage DAC12...
Page 812 DAC12 Registers DAC12_xDAT, DAC12 Data Register DAC12 Data r(0) r(0) r(0) r(0) rw−(0) rw−(0) rw−(0) rw−(0) DAC12 Data rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Unused Bits Unused. These bits are always 0 and do not affect the DAC12 core. 15-12 DAC12 Data Bits...
Page 813 Chapter 30 Scan IF The Scan IF peripheral automatically scans sensors and measures linear or rotational motion. This chapter describes the Scan interface. The Scan IF is implemented in the MSP430FW42x devices. Topic Page 30.1 Scan IF Introduction ......... . 30-2 30.2 Scan IF Operation .
Page 814: Scan If Introduction
Scan IF Introduction 30.1 Scan IF Introduction The Scan IF module is used to automatically measure linear or rotational motion with the lowest possible power consumption. The Scan IF consists of three blocks: the analog front end (AFE), the processing state machine (PSM), and the timing state machine (TSM).
Page 815 Scan IF Introduction Figure 30−1. Scan IF Block Diagram Scan I/F Analog Front−End To Timer_A (AFE) SIFCI SIFCI3 Interrupt SIFCI2 Request SIFCI1 Processing State SIFCI0 Machine (PSM) Rotation SIFCH3 Data SIFCH2 − Excit SIFCH1 SIFCH0 SIFCOM Timing State DAC 10 Bit Machine (TSM) ACLK SIFVSS...
Page 816: Scan If Operation
Scan IF Operation 30.2 Scan IF Operation The Scan IF is configured with user software. The setup and operation of the Scan IF is discussed in the following sections. 30.2.1 Scan IF Analog Front End The Scan IF analog front end provides sensor excitation and measurement. The analog front end is automatically controlled by the timing state machine according to the information in the timing state machine table.
Page 817 Scan IF Operation Figure 30−2. Scan IF Analog Front End Block Diagram SIFCISEL SIFCACI3 SIFCI SIFCAINV SIFCI3 Output Stage SIFCI2 SIFRSON(tsm) SIFCI1 SIFCA(tsm) SIFCI0 SIFVSS SIFCAON SIF0OUT SIFCAX Sample/Hold SIF1OUT SIFSH SIF2OUT SIFCH3 SIF3OUT SIFCH2 SIFCH1 − SIFCH0 SIFDAC(tsm) SIFTCH0OUT SIFDACON SIFTCH1OUT DAC 10 Bit...
Page 818 Scan IF Operation Excitation The excitation circuitry is used to excite the LC sensors or to power the resistor dividers. The excitation circuitry is shown in Figure 30−3 for one LC sensor connected. When the SIFTEN bit is set and the SIFSH bit is cleared the excitation circuitry is enabled and the sample-and-hold circuitry is disabled.
Page 819 Scan IF Operation Figure 30−3. Excitation and Sample-And-Hold Circuitry SIFSH SIFCH0 Comparator SIFVSS SIFCOM SIFEX(tsm) Sample-and-Hold Damping SIFLCEN(tsm) SIFTEN From Channel Excitation Select Logic Excitation SIFVCC2 VMID Gen Scan IF 30-7...
Page 820 Scan IF Operation Sample-And-Hold The sample-and-hold is used to sample the sensor voltage to be measured. The sample-and-hold circuitry is shown in Figure 30−3. When SIFSH = 1 and SIFTEN = 0 the sample-and-hold circuitry is enabled and the excitation circuitry and mid-voltage generator are disabled.
Page 821 Scan IF Operation Direct Analog And Digital Inputs By setting the SIFCAX bit, external analog or digital signals can be connected directly to the comparator through the SIFCIx inputs. This allows measurement capabilities for optical encoders and other sensors. Comparator Input Selection And Output Bit Selection The SIFCAX and SIFSH bits select between the SIFCIx channels and the SIFCHx channels for the comparator input as described in Table 30−1.
Page 822 Scan IF Operation When SIFCAX = 1, the SIFCSEL and SIFCI3 bits select between the SIFCIx channels and the SIFCI input allowing storage of the comparator output for one input signal into the four output bits SIF0OUT - SIF3OUT. This can be used to observe the envelope function of sensors.
Page 823 Scan IF Operation Comparator and DAC The analog input signals are converted into digital signals by the comparator and the programmable 10-bit DAC. The comparator compares the selected analog signal to a reference voltage generated by the DAC. If the voltage is above the reference the comparator output will be high.
Page 824 Scan IF Operation For each input there are two DAC registers to set the reference level as listed in Table 30−3. Together with the last stored output of the comparator, SIFxOUT, the two levels can be used as an analog hysteresis as shown in Figure 30−6.
Page 825 Scan IF Operation Internal Signal Connections to Timer1_A5 The outputs of the analog front end are connected to 3 different capture/compare registers of Timer1_A5. The output stage of the analog front end, shown in Figure 30−7. provides two different modes that are selected by the SIFCS bit and provides the SIFOx signals to Timer1_A5.
Page 826: Scan If Timing State Machine
Scan IF Operation 30.2.2 Scan IF Timing State Machine The TSM is a sequential state machine that cycles through the SIFTSMx registers and controls the analog front end and sensor excitation automatically with no CPU intervention. The states are defined within a 24 x 16-bit memory, SIFTSM0 to SIFTSM23.
Page 827 Scan IF Operation Figure 30−8. Timing State Machine Block Diagram SIFDIV3Ax SIFDIV2x SIFDIV3Bx Set_SIFIFG2 Divider Divider ACLK /2 .. /450 /1/2/4/8 SIFTSM0 SIFEN SIFTSMRP SIFTSM1 SIFCHx(tsm) SIFCH0 Start SIFCH1 SIFLCOFF(tsm) SIFLCOFF SIFEX(tsm) SIFEX ACLK SIFCA SIFCA(tsm) SIFCLKON SIFCLKON(tsm SIFRSON(tsm) SIFRSON State Pointer SIFDIV1x SIFCLKEN...
Page 828 Scan IF Operation TSM Operation The TSM automatically starts and re-starts periodically based on a divided ACLK start signal selected with the SIFDIV2x bits, the SIFDIV3Ax and SIFDIV3Bx bits when SIFTSMRP = 0. For example, if SIFDIV3A and SIFDIV3B are configured to 270 ACLK cycles, then the TSM automatically starts every 270 ACLK cycles.
Page 829 Scan IF Operation TSM State Clock Source Select The TSM clock source is individually configurable for each state. The TSM can be clocked from ACLK or a high frequency clock selected with the SIFACLK bit. When SIFACLK = 1, ACLK is used for the state, and when SIFACLK = 0, the high frequency clock is used.
Page 830 Scan IF Operation TSM Test Cycles For calibration purposes, to detect sensor drift, or to measure signals other than the sensor signals, a test cycle may be inserted between TSM cycles by setting the SIFTESTD bit. The time between the TSM cycles is not altered by the test cycle insertion as shown in Figure 30−9.
Page 831 Scan IF Operation TSM Example Figure 30−10 shows an example for a TSM sequence. The TSMx register values for the example are shown in Table 30−6. ACLK and SIFCLK are not drawn to scale. The TSM sequence starts with SIFTSM0 and ends with a set SIFSTOP bit in SIFTSM9.
Page 832: Scan If Processing State Machine
Scan IF Operation 30.2.3 Scan IF Processing State Machine The PSM is a programmable state machine used to determine rotation and direction with its state table stored within MSP430 memory (flash, ROM, or RAM). The processing state machine measures rotation and controls interrupt generation based on the inputs from the timing state machine and the analog front-end.
Page 833 Scan IF Operation Figure 30−11.Scan IF Processing State Machine Block Diagram SIFS1x SIF0OUT SIF1OUT SIF2OUT SIF3OUT MSP430 SIFS2x Memory Range State Latch Output SIFIS1x SIFCNT1ENP SIFEN Latch State Table Δ1 Δ4 Set_SIFIFG3 Q7 . . . Q0 SIFCNT1 Δ64 Δ256 −1 SIFQ6EN SIFCNTRST...
Page 834 Scan IF Operation Signals S1 and S2 form a 2-bit offset added to the SIFPSMV contents to determine the first byte loaded to the PSM output latch. For example, when S2 = 1, and S1 = 0, the first byte loaded by the PSM will be at the address SIFPSMV + 2.
Page 835 Scan IF Operation PSM Counters The PSM has two 8-bit counters SIFCNT1 and SIFCNT2. SIFCNT1 is updated with Q1 and Q2 and SIFCNT2 is updated with Q2. The counters can be read via the SIFCNT register. If the SIFCNTRST bit is set, each read access will reset the counters, otherwise the counters remain unchanged when read.
Page 836 Scan IF Operation Simplest State Machine Figure 30−12 shows the simplest state machine that can be realized with the PSM. The following code shows the corresponding state table and the PSM initialization. Figure 30−12. Simplest PSM State Diagram S1=0 & S2=0 State 00 00000000 S1=1 &...
Page 837 Scan IF Operation If the PSM is in state 01 of the simplest state machine and the PSM has loaded the corresponding byte at index 01h of the state table: For this example, S1 and S2 are set at the end of the next TSM sequence. To calculate the next state the bits Q5 - Q3 and Q0 of the state 01 table entry, together with the S1 and S2 signals are combined to form the next state: The state table entry for state 11 is loaded at the next state transition:...
Page 838: Scan If Debug Register
Scan IF Operation 30.2.4 Scan IF Debug Register The Scan IF peripheral has a SIFDEBUG register for debugging and development. Only the lower two bits should be written when writing to the SIFDEBUG register and only MOV instructions should be used write to SIFDEBUG.
Page 839: Scan If Interrupts
Scan IF Operation 30.2.5 Scan IF Interrupts The Scan IF has one interrupt vector for seven interrupt flags listed in Table 30−7. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt.
Page 840: Using The Scan If With Lc Sensors
Scan IF Operation 30.2.6 Using the Scan IF with LC Sensors Systems with LC sensors use a disk that is partially covered with a damping material to measure rotation. Rotation is measured with LC sensors by exciting the sensors and observing the resulting oscillation. The oscillation is either damped or un-damped by the rotating disk.
Page 841 Scan IF Operation 30.2.6.1 LC-Sensor Oscillation Test The oscillation test tests if the amplitude of the oscillation after sensor excitation is above a reference level. The DAC is used to set the reference level for the comparator, and the comparator detects if the LC sensor oscillations are above or below the reference level.
Page 842 Scan IF Operation 30.2.6.2 LC-Sensor Envelope Test The envelop test measures the decay time of the oscillations after sensor excitation. The oscillation envelope is created by the diodes and RC filters. The DAC is used to set the reference level for the comparator, and the comparator detects if the oscillation envelop is above or below the reference level.
Page 843 Scan IF Operation Figure 30−17. LC Sensor Connections For The Envelope Test SIFCI SIFCI3 SIFCI2 SIFCI1 SIFCI0 SIFCH3 SIFCH2 SIFCH1 SIFCH0 SIFCOM 470 nF SIFVSS Power 470 nF Supply Terminals Scan IF 30-31...
Page 844: Using The Scan If With Resistive Sensors
Scan IF Operation 30.2.7 Using the Scan IF With Resistive Sensors Systems with GMRs use magnets on an impeller to measure rotation. The damping material and magnets modify the electrical behavior of the sensor so that rotation and direction can be detected. Rotation is measured with resistive sensors by connecting the resistor dividers to ground for a short time allowing current flow through the dividers.
Page 845: Quadrature Decoding
Scan IF Operation 30.2.8 Quadrature Decoding The Scan IF can be used to decode quadrature-encoded signals. Signals that are 90° out of phase with each other are said to be in quadrature. To Create the signals, two sensors are positioned depending on the slotting, or coating of the encoder disk.
Page 846 Scan IF Operation Figure 30−20. Quadrature Decoding State Diagram −1 Correct State Transitions Erroneous State Transitions To transfer the state encoding into counts it is necessary to decide what fraction of the rotation should be counted and on what state transitions. In this example only full rotations will be counted on the transition from state 00 to 01 or 10 using a 180°...
Page 847: Scan If Registers
Scan IF Registers 30.3 Scan IF Registers The Scan IF registers are listed in Table 30−9. Table 30−9.Scan IF Registers Register Short Form Register Type Address Initial State Scan IF debug register SIFDEBUG Read/write 01B0h Unchanged Scan IF counter 1 and 2 SIFCNT Read/write 01B2h...
Page 848 Scan IF Registers SIFDEBUG, Scan IF Debug Register, Write Mode Reserved Reserved SIFDEBUGx Reserved Bits Reserved. Must be written as zero. 15-2 SIFDEBUGx Bits SIFDEBUG register mode. Writing these bits selects the read-mode of the SIFDEBUG register. SIFDEBUG must be written with MOV instructions only. When read, SIFDEBUG shows the last address read by the PSM When read, SIFDEBUG shows the value of the TSM state pointer and the PSM bits Q7 - Q0...
Page 849 Scan IF Registers SIFDEBUG, Scan IF Debug Register, Read Mode After 01h Is Written Index Of TSM Register PSM Bits Q7 − Q0 Unused Bits Unused. After 01h is written to SIFDEBUG, these bits are always read as zero. 15-13 TSM Index Bits When SIFDEBUG is read, after 01h is written to it, these bits show the TSM...
Page 850 Scan IF Registers SIFDEBUG, Scan IF Debug Register, Read Mode After 03h Is Written Active DAC Register DAC Data DAC Data Unused Bit 15 Unused. After 03h is written to SIFDEBUG, this bit is always read as zero. Bits When SIFDEBUG is read, after 03h is written to it, these bits show which DAC Register 14-12 register is currently selected to control the DAC.
Page 851 Scan IF Registers SIFCNT, Scan IF Counter Register SIFCNT2x r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) SIFCNT1x r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) r−(0) SIFCNT2x Bits SIFCNT2. These bits are the SIFCNT2 counter. SIFCNT2 is reset when 15-8 SIFEN = 0 or if read when SIFCNTRST = 1.
Page 852 Scan IF Registers SIFCTL1, Scan IF Control Register 1 SIFIE6 SIFIE5 SIFIE4 SIFIE3 SIFIE2 SIFIE1 SIFIE0 SIFIFG6 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFIFG5 SIFIFG4 SIFIFG3 SIFIFG2 SIFIFG1 SIFIFG0 SIFTESTD SIFEN rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFIEx Bits...
Page 853 Scan IF Registers SIFIFG0 Bit 2 SIF interrupt flag 0. This bit is set by the SIFxOUT conditions selected by the SIFIFGSETx bits. SIFIFG0 must be reset with software. No interrupt pending Interrupt pending SIFTESTD Bit 1 Test cycle insertion. Setting this bit inserts a test cycle between TSM cycles. SIFTESTD is automatically reset at the end of the test cycle.
Page 854 Scan IF Registers SIFCTL2, Scan IF Control Register 2 SIFDACON SIFCAON SIFCAINV SIFCAX SIFCISEL SIFCACI3 SIFVSS SIFVCC2 rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFTCH1 SIFTCH0 SIFSH SIFTEN SIFTCH1x SIFTCH0x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFDACON Bit 15 DAC on.
Page 855 Scan IF Registers SIFVCC2 Bit 8 Mid-voltage generator /2 generator is off /2 generator is on if SIFSH = 0 SIFSH Bit 7 Sample-and-hold enable Sample-and-hold is disabled Sample-and-hold is enabled SIFTEN Bit 6 Excitation enable Excitation circuitry is disabled Excitation circuitry is enabled SIFTCH1x Bits...
Page 856 Scan IF Registers SIFCTL3, Scan IF Control Register 3 SIFS2x SIFS1x SIFIS2x SIFIS1x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFCS SIFIFGSETx SIF3OUT SIF2OUT SIF1OUT SIF0OUT rw−(0) rw−(0) rw−(0) rw−(0) r−(0) r−(0) r−(0) r−(0) SIFS2x Bits S2 source select. These bits select the S2 source for the PSM when SIFCS 15-14 = 1.
Page 857 Scan IF Registers SIFIFGSETx Bits SIFIFG0 interrupt flag source. These bits select when the SIFIFG0 flag is set. 000 SIFIFG0 is set when SIF0OUT is set. 001 SIFIFG0 is set when SIF0OUT is reset. 010 SIFIFG0 is set when SIF1OUT is set. 011 SIFIFG0 is set when SIF1OUT is reset.
Page 858 Scan IF Registers SIFCTL4, Scan IF Control Register 4 SIFCNT1 SIFCNT1 SIFCNTRST SIFCNT2EN SIFQ7EN SIFQ6EN SIFDIV3Bx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFDIV3Bx SIFDIV3Ax SIFDIV2x SIFDIV1x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFCNTRST Bit 15 Counter reset. Setting this bit enables the SIFCNT register to be reset when it is read.
Page 859 Scan IF Registers SIFDIV3Bx Bits TSM start trigger ACLK divider. These bits together with the SIFDIV3Ax bits select the division rate for the TSM start trigger. SIFDIV3Ax Bits TSM start trigger ACLK divider. These bits together with the SIFDIV3Bx bits select the division rate for the TSM start trigger.
Page 860 Scan IF Registers SIFCTL5, Scan IF Control Register 5 SIFCNT3x rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFCLKG SIFTSMRP SIFCLKFQx SIFFNOM SIFCLKEN rw−(0) rw−(1) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFCNT3x Bits Internal oscillator counter. SIFCNT3 counts internal oscillator clock cycles 15-8 during one ACLK period when SIFFNOM = 0 or during four ACLK periods when SIFFNOM = 1 after SIFCLKGON and SIFCLKEN are both set...
Page 861 Scan IF Registers SIFDACRx, Digital-To-Analog Converter Registers DAC Data DAC Data Unused Bits Unused. These bits are always read as zero, and when written, do not affect 15-10 the DAC output. DAC Data Bits 10-bit DAC data Scan IF 30-49...
Page 862 Scan IF Registers SIFTSMx, Scan IF Timing State Machine Registers SIFREPEATx SIFACLK SIFSTOP SIFDAC rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) SIFTESTS1 SIFRSON SIFCLKON SIFCA SIFEX SIFLCEN SIFCHx rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) Bits These bits together with the SIFACLK bit configure the duration of this state. REPEATx 15-11 SIFREPEATx selects the number of clock cycles for this state.
Page 863 Scan IF Registers SIFCLKON Bit 5 High-frequency clock on. Setting this bit turns the high-frequency clock source on for this state when SIFACLK = 1, even though the high frequency clock is not used for the TSM. When the high-frequency clock is sourced from the DCO, the DCO is forced on for this state, regardless of the MSP430 low-power mode.
Page 864 Scan IF Registers Processing State Machine Table Entry (MSP430 Memory Location) Bit 7 When Q7 = 1, SIFIFG6 will be set. When SIFQ6EN = 1 and SIFQ7EN = 1 and Q7 = 1, the PSM proceeds to the next state immediately, regardless of the SIFSTOP(tsm) signal and Q7 is used in the next-state calculation.
Page 865: Embedded Emulation Module (Eem)
Chapter 31 Embedded Emulation Module (EEM) This chapter describes the Embedded Emulation Module (EEM) that is implemented in all MSP430 flash devices. Topic Page 31.1 EEM Introduction ..........31-2 31.2 EEM Building Blocks .
Page 866: Eem Introduction
EEM Introduction 31.1 EEM Introduction Every MSP430 flash-based microcontroller implements an embedded emulation module (EEM). It is accessed and controlled through JTAG. Each implementation is device dependent and is described in section 31.3 EEM Configurations and the device data sheet. In general, the following features are available: Nonintrusive code execution with real-time breakpoint control Single step, step into, and step over functionality...
Page 867 EEM Introduction Figure 31−1. Large Implementation of the Embedded Emulation Module (EEM) Trigger ”AND” Matrix − Combination Triggers Blocks CPU0 CPU1 & & & & & & & & Trigger Sequencer CPU Stop Start/Stop State Storage Embedded Emulation Module (EEM) 31-3...
Page 868: Eem Building Blocks
EEM Introduction 31.2 EEM Building Blocks 31.2.1 Triggers The event control in the EEM of the MSP430 system consists of triggers, which are internal signals indicating that a certain event has happened. These triggers may be used as simple breakpoints, but it is also possible to combine two or more triggers to allow detection of complex events and trigger various reactions besides stopping the CPU.
Page 869: Trigger Sequencer
EEM Introduction 31.2.2 Trigger Sequencer The trigger sequencer allows the definition of a certain sequence of trigger signals before an event is accepted for a break or state storage event. Within the trigger sequencer, it is possible to use the following features: Four states (State 0 to State 3) Two transitions per state to any other state Reset trigger that resets the sequencer to State 0.
Page 870: Eem Configurations
EEM Configurations 31.3 EEM Configurations Table 31−1 gives an overview of the EEM configurations in the MSP430 4xx family. The implemented configuration is device dependent (see the device-specific data sheet. Table 31−1.4xx EEM Configurations Feature Memory Bus Triggers =, ≠ only) Memory Bus Trigger Mask for 1) Low byte...
Page 871 TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products...

Texas Instruments MSP430x4xx Family User Manual

1 Introduction

2 System Resets, Interrupts, and Operating Modes

3 RISC 16-Bit CPU

16 Bit MSP430X CPU

5 FLL+ Clock Module

6 Flash Memory Controller

7 Supply Voltage Supervisor

8 16-Bit Hardware Multiplier

Bit Hardware Multiplier

10 DMA Controller

11 Digital I/O

12 Watchdog Timer, Watchdog Timer+

13 Basic Timer1

14 Real Time Clock

15 Timer_A

16 Timer_B

17 USART Peripheral Interface, UART Mode

18 USART Peripheral Interface, SPI Mode

19 Universal Serial Communication Interface, UART Mode

20 Universal Serial Communication Interface, SPI Mode

21 Universal Serial Communication Interface, I2C Mode

22 Oa

23 Comparator_A

24 LCD Controller

25 LCD_A Controller

26 Adc12

27 Sd16

28 Sd16_A

29 Dac12

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Summary of Contents for Texas Instruments MSP430x4xx Family