Clocks And Oscillators; User Interface; Codec Ssi Bus; Spi Bus - Motorola APX 7500 Detailed Service Manual

Theory of Operation: System Communications Overview
2.3.5

Clocks and Oscillators

The controller clock distribution consists of several primary clock sources:
• 32.768kHz
- Crystal oscillator (Y402) is used as a startup clock provided to the OMAP processor
(U400). An additional 32.768kHz crystal (Y1601) is placed to provide a reference signal to
the Real-Time Clock IC (U1601). These two oscillators must be separate due to differing
circuit requirements for crystal load capacitance.
• 12MHz
- Crystal oscillator (Y401) provides the base clock source to the OMAP processor (U400).
The OMAP DPLL then multiplies this base frequency to generate the DSP clock, MPU
clock, etc. This clock is also used as the reference for all internal OMAP clocks
synthesized by its internal PLL, such as the FLASH and SDRAM clocks and serial bus
timing.
• 16MHz
- A 16MHz reference clock is provided to the Nautilus FPGA by crystal oscillator Y901.
• 25MHz
- Provided by the dedicated oscillator, Y701, to the Ethernet LAN Controller IC (U704).
2.3.6

User Interface

The user interface consists of the O5 control head, 19 buttons, and a GCAI connector. In addition,
user feedback is provided using a 131 x 53 pixel LCD and a bi-color LED. One of the buttons is used
for the Speaker_Mute function. This input will disable and re-enable the local speaker audio. Three
of the buttons are grouped together and used for the LCD softkeys, three others are used as
programmable buttons. The remaining buttons are alphanumeric and provide inputs to the keypad
controller inside the microprocessor.
2.3.7

CODEC SSI Bus

The CODEC SSI is a dedicated bus for the TLVAIC12K CODEC. It has a 512 kHz clock, 8 kHz frame
sync, 16 bit word size, and four slots. The FPGA transfers data from the CAN1 bus to the dedicated
SSI Bus. The CODEC then provides signal conversion from digital to analog (D/A) and from analog
to digital (A/D). The FPGA is the clock master, generating the clock and frame sync.
CODEC SSI Signals:
• SCLK_CODEC
• STDA_CODEC
• SRDA_CODEC
• FS_CODEC
• MCLK_CODEC
• PWRDN_CODEC
• RESET*-CODEC
2.3.8

SPI Bus

OMAP programs the FPGA at power-on via the SPI interface. OMAP also uses the SPI bus to read
and write FPGA registers. The audio attenuation IC is also programmed using the SPI bus.
SPI Signals:
• SPI_CS: SPI FPGA Chip select.
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September 9, 2011