Pci Latency Timer (Clk); Maximum Payload Size - Acer Aspire AM5610 Service Manual

PCI Latency Timer (CLK)

This item controls how long a PCI device can hold the PCI bus before another device takes over. Setting the
latency to longer periods enbles a PCI device to retain control of the bus longer before handing it over to another
device.

Maximum Payload Size

This BIOS feature determines the maximum TLP (Transaction Layer Packet) payload size that can be supported
by the motherboard chipset's PCI Express controller. The TLP payload size determines the amount of data
transmitted within each data packet. When set to 4096, the motherboard chipset's PCI Express controller supports
the maximum data payload of 4096 bytes within each TLP. This is the maximum payload size currently supported
by the PCI Express protocol.
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