Schematic Diagram - Yamaha YSP-800 Service Manual

A B C
SCHEMATIC DIAGRAM (DSP 1/3)
1
2
0.3
0
5.0
0
3.4
3.2
DIR
3
3.4
0
Page 56 C3
to DSP_CB6
4
5
0.1
1.4
0
3.4
3.4
3.4
0
1.4
0.1
1.4
0
0.1
0.1
6
1.7
1.4
0
1.7
3.4
0
1.4
0
3.1
3.3
3.3
0
1.4
2.6
7
0
1.4
3.4
3.4
3.4
0
1.4
3.4
0
0
1.4
1.4
0
8
9
10
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
D E F
3.4
0
0
0
0
3.4
1.6
1.6
A-2
1.6 F.F
3.4
0
0
3.3
3.3
2.6
2.6
3.4
0
3.4
0
DSP1
1.4
G H I
3.3
0
3.2
3.2
1.2
1.2
3.3 0
4.8
1.7 1.7
1.7 1.7
0 0
2.5 0
2.5 5.0
2.5 2.5
3.4
1.7
0
1.7
1.2
3.3
1.3
1.4
0
3.3
0.7
1.3
0
0
0
3.4
1.7
1.7
3.4
0
1.4
3.2
3.2
3.2
3.3
3.2
3.2
3.4
0
1.4
3.2
3.2
3.2
5.2
3.4 0
3.2 3.2
3.2
3.2 3.2 3.3
3.4 0 0
1.4 3.2 3.2
0
3.3 3.2
3.4 3.2 3.4
3.2 3.2 3.4
3.2 3.2 3.2
3.2 0 0
3.2 3.2 3.2
3.2 3.2
3.2 3.3 3.4
3.4 3.2
0 3.3 3.2
1.4 3.3 1.7
3.3 3.3
3.3
0.3 0
0 0
0 2.9
0 2.6
3.3 1.7
3.3 2.7
0
3.4
DRAM
POINT A-2 pin 29 of IC4
J K
IC1~3: PQ1CZ41H2Z
Chopper Regulators
V
IN
1
Voltage ON/OFF
regulator circuit
PWM COMP.
Q
Overcurrent
R
detection F/F
circuit S
ERROR AMP.
V
ref
Overheat
detection
circuit
3
COM
IC4: LC89057W-VF4D-E
Digital Audio Interface Transceiver
EMPHA/UO AUDIO/VO INT CL CE CI
32 33 35 48 39 38 41
RXOUT 1 Microcontroller
Cbit, Ubit
I/F
RX0 2
RX1 3
RX2 4
Demodulation
Input
Data
RX3 5 &
Selector
Selector
Lock detect
RX4 8
RX5/VI 9
RX6/UI 10
PLL
LPF 13
Clock
TMCK/PIO0 44
Selector
Modulation
TBCK/PIO1 45
1/N
&
TLRCK/PIO2 46
Parallel Port
TDATA/PIO3 47
TXO/PIOEN 48
29 28 27 34
XIN XOUT XMCK CKST
IC5: D60YA003BPYP225
Decoder
Digital Signal Processors
EMIF32 L2 Cache/
L1P Cache
Memory
4 Banks Direct Mapped
McASP1 64K Bytes 4K Bytes Total
Total
McASP0
(4-Way)
C67x
McBSP1
Instruction Fetch
McBSP0 Instruction Dispatch
L2 Instruction Decode
I2C1 Enhanced
Memory
DMA Data Path A Data Path B
Controller
I2C0 DA610:
(16 channel) A Register File B Register File
192K Bytes
Timer 1
DA601:
64K Bytes .L1t .S1t .M1t .D1 .D2 .M2t .S2t .L2t
Timer 0
GP1
L1D Cache
2-Way Set
GP0
R2 ROM
Associative
512K
4K Bytes Total
HPI16 Bytes
Total
Clock Generator,
Oscillator and PLL
x4 through x25 Multipliers
/1 through /32 Dividers
IC10: WM8738
24bit Stereo ADC
0 0
0 3.4
0 0
6 4 11
0 3.2
AVDD 9
0.3 3.2
CONTROL
0 3.3
INTERFACE
0 3.2
CAP 5
0 3.2
3.2
AGND 10
3.2
3.3 3.2
0 3.4 RIN 7 ADC 2 SDATO
3.4
3.3
12 LRCLK
3.2 DIGITAL AUDIO
0
3.2
FILTERS INTERFACE
3.2 3 BCLK
0
2.9 3.2
2.6 3.2
ADC 13 MCLK
LIN 8
1.7 3.2
2.7 3.3
3.3 0
3.3 3.3
0 0
1 14
FLASH
IC7: SN74LVC74APWR
DSP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
PRE
C
CLK C
C
TG
C C C
C
D TG TG TG
C C C
CLR
L M N
YSP-800
IC9: W9816G6CH
512K x 2 Banks x 16 Bits SDRAM
V
OUT
CLK 35
2 CLOCK
BUFFER
CKE 34
COLUMN DECODER
ON/OFF CS 18 CONTROL
5 SIGNAL
control R
RAS 17 GENERATOR O
COMMAND
W
CAS 16 DECODER
D CELL ARRAY
2 DQ0
E
WE 15 BANK #0
C
3 DQ1
O
D
5 DQ2
E
R
O
adj A10 20 6 DQ3
4
SENSE AMPLIFIER
8 DQ4
9 DQ5
MODE
A0 21 11 DQ6
∼ REGISTER
ADDRESS 12 DQ7
A3 24
REFRESH DQ
BUFFER
COUNTER BUFFER 39 DQ8
A4 27
∼
40 DQ9
A9 32
42 DQ10
BA 19
43 DQ11
45 DQ12
46 DQ13
REFRESH COLUMN
COLUMN DECODER
48 DQ14
COUNTER COUNTER
R
49 DQ15
O
W
XMODE
D CELL ARRAY
E
BANK #1
C
O
D
E
14 LDQM
R
36 UDQM
SENSE AMPLIFIER
37 DO
36 RERR
21 RDATA
24 SDIN
IC6: SN74AHC1G08DCKR
16
RMCK
2-input positive-AND gate
17 RBCK
20 RLRCK
22 SBCK
23 SLRCK A 1 5 Vcc
B 2
GND 3 4 Y
IC8: SN74LV245APWR
Octal Bus Transceivers with 3-state Outputs
DIR 1 20 Vcc
A1 2 19 OE
A2 3 18 B1
TM CPU
Control
A3 4 17 B2
Registers
Control
Logic A4 5 16 B3
Test
A5 6 15 B4
In-Circuit
Emulation
A6 7 14 B5
Interrupt
Control
A7 8 13 B6
A8 9 12 B7
GND 10 11 B8
Power-Down
Logic
IC11: MBM29LV400BC
FLASH MEMORY
DQ to DQ
0 15
RY/BY
RY/BY
Buffer
V
CC
V SS Erase Voltage Input/Output
Generator Buffers
WE
State
BYTE Control
RESET
Command
Register
Program Voltage
Generator Chip Enable
STB
Output Enable Data Latch
Logic
CE
OE
Y-Decoder Y-Gating
STB
Timer for
Low V Detector Address
CC Program/Erase
Latch
X-Decoder Cell Matrix
A to A
0 17
A
-1
1CLR VCC
1 14
Q
1D 2 13 2CLR
1CLK 3 12 2D
1PRE 2CLK
4 11
1Q 5 10 2PRE
1Q 6 9 2Q
7 8
GND 2Q
Q
55