Mac Input Vector Register (Macinvector); Mac Input Vector Register (Macinvector) Field Descriptions - Texas Instruments TMS320C6745 DSP Reference Manual

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17.3.3.11 MAC Input Vector Register (MACINVECTOR)

The MAC input vector register (MACINVECTOR) is shown in
31 28
Reserved
R-0
15
LEGEND: R = Read only; -n = value after reset
Table 17-48. MAC Input Vector Register (MACINVECTOR) Field Descriptions
Bit Field
31-28 Reserved
27 STATPEND
26 HOSTPEND
25 LINKINT0
24 USERINT0
23-16 TXPEND
15-8 RXTHRESHPEND
7-0 RXPEND
SPRUH91D – March 2013 – Revised September 2016
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Figure 17-49. MAC Input Vector Register (MACINVECTOR)
27 26
STATPEND HOSTPEND LINKINT0
R-0 R-0
RXTHRESHPEND
R-0
Value Description
0 Reserved
0-1 EMAC module statistics interrupt (STATPEND) pending status bit
0-1 EMAC module host error interrupt (HOSTPEND) pending status bit
0-1 MDIO module USERPHYSEL0 (LINKINT0) status bit
0-1 MDIO module USERACCESS0 (USERINT0) status bit
0-FFh Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND.
0-FFh Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. Bit 8 is
RX0THRESHPEND.
0-FFh Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND.
Copyright © 2013–2016, Texas Instruments Incorporated
Figure 17-49
25 24 23
USERINT0
R-0 R-0
8 7
Registers
and described in Table 17-48.
TXPEND
R-0
RXPEND
R-0
EMAC/MDIO Module
16
0
655