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iSBC® 80/30 SINGLE BOARD COMPUTER
slave processor to the iSBC 80/30's 808SA CPU.
The UPI allows the user to specifiy algorithms for
controlling user peripherals directly in the chip,
thereby relieving the 8085A for other system func-
tions. The iSBC 80/30 provides an RS232C driver
and an RS232C receiver for optional connection to
the 8041A/8741A in applications where the UPI is
programmed to handle simple serial interfaces. For
additional information, including 8041A/8741A in-
structions, refer to the UPI-41 A User's Manual and
application note AP-41.
Serial 1/0
A programmable communications interface using
the Intel 8251 A Universal Synchronous/ Asynchro-
nous Receiver/Transmitter (USART) is contained on
the iSBC 80/30. A software selectable baud rate
generator provides the USART with all common
communication frequencies. The USART can be
programmed by the system software to select the
desired asynchronous or synchronous serial data
transmission technique (including IBM By-Sync).
The mode of operation (Le., synchronous or asyn-
chronous), data format, control character format,
parity, and baud rate are all under program control.
The 8251 A provides full duplex, double buffered
transmit and receive capability. Parity, overrun, and
framing error detection are all incorporated in the
USART. The RS232C compatible interface on each
board, in conjunction with the USART, provides a
direct interface to RS232C compatible terminals,
cassettes, and asynchronous and synchronous mo-
dems. The RS232C command lines, serial data
lines, and signal ground line are brought out to a 26-
pin edge connector that mates with RS232C com-
patible flat or round cable.
Multimaster Capability
The iSBC 80/30 is a full computer on a single board
with resources capable of supporting a great variety
of OEM system requirements. For those applications
requiring additional processing capacity and the
benefits of multiprocessing (Le., several CPUs and/
or controilers logically sharing system tasks through
communication over the system bus), the iSBC
80/30 provides full MUL TIBUS arbitration control
logic. This control logic allows up to three iSBC 80/
30's or other bus masters to share the system bus in
serial (daisy chain) priority fashion, and up to 16
masters to share the MUL TIBUS with the addition of
an external priority network. The MUL TIBUS arbitra-
tion logic operates synchronously with a MUL TIBUS
clock (provided by the iSBC 80/30 or optionally con-
nected directly to the MUL TIBUS clock) while data is
transferred via a handshake between the master
and slave modules. This allows different speed con-
trollers to share resources on the same bus, and
transfer via the bus proceed asynchronously. Thus,
transfer speed is dependent on transmitting and re-
ceiving devices only. This design prevents slow
master modules from being handicapped in their at-
tempts to gain control of the bus, but does not re-
strict the speed at which faster moqules can transfer
data via the same bus. The most obvious applica-
tions for the master-slave capabilities of the bus are
multiprocessor configurations, high speed direct
memory access (DMA) operations, and high speed
peripheral control, but are by no means limited to
these three.
Programmable Timers
The iSBC 80/30 provides three independent, fully
programmable 16-bit interval timers/event counters
utilizing the Intel 8253 Programmable Interval Timer.
Each counter is capabile of operating in either BCD
or binary modes. Two of these timers/counters are
available to the systems designer to generate accu-
rate time intervals under software control. Routing
for the outputs and gate/trigger inputs of two of
,these counters is jumper selectable. The outputs
may be independently
route~
to the 82S9A Program-
Mode of Operation
Lines
Unidirectional
Port
(qty)
Input
Output
Control
Bidirectional
Unlatched
Latched &
Latched
Latched &
Strobed
Strobed
1
8
X
X
X
X
X
2
8
X
X
X
X
3
4
X
X
X1
4
X
X
X1
NOTE:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.
3-29
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