Toshiba 40L7363RK Service Manual page 47

128. DDR3 B Resistors
Adding 0[ohm] Resistor
M_B_DDR3_DQ10 M_B_DDR3_DQ10
127
M_B_DDR3_DQ14 M_B_DDR3_DQ14
127
M_B_DDR3_DQ8 M_B_DDR3_DQ8
127
M_B_DDR3_DQ12 M_B_DDR3_DQ12
127
M_B_DDR3_DQ15 M_B_DDR3_DQ15
127
M_B_DDR3_DQ9 M_B_DDR3_DQ9
127
M_B_DDR3_DQ11 M_B_DDR3_DQ11
127
M_B_DDR3_DQM1 M_B_DDR3_DQM1
127
M_B_DDR3_DQM0 M_B_DDR3_DQM0
127
M_B_DDR3_DQ3 M_B_DDR3_DQ3
127
M_B_DDR3_DQ1 M_B_DDR3_DQ1
127
M_B_DDR3_DQ7 M_B_DDR3_DQ7
127
M_B_DDR3_DQ0 M_B_DDR3_DQ0
127
M_B_DDR3_DQ2 M_B_DDR3_DQ2
127
M_B_DDR3_DQ6 M_B_DDR3_DQ6
127
M_B_DDR3_DQ4 M_B_DDR3_DQ4
127
M_B_DDR3_DQ13 M_B_DDR3_DQ13
R1284 R1284
127
M_B_DDR3_DQ5 M_B_DDR3_DQ5
R1285 R1285
127
RM145 RM145 0 OHM 0 OHM
S_B_DDR3_DQ10 S_B_DDR3_DQ10
1 8
S_B_DDR3_DQ14 S_B_DDR3_DQ14
2 7
S_B_DDR3_DQ8 S_B_DDR3_DQ8
3 6
S_B_DDR3_DQ12 S_B_DDR3_DQ12
4 5
RM146 RM146 0 OHM 0 OHM
S_B_DDR3_DQ15 S_B_DDR3_DQ15
1 8
S_B_DDR3_DQ9 S_B_DDR3_DQ9
2 7
S_B_DDR3_DQ11 S_B_DDR3_DQ11
3 6
S_B_DDR3_DQM1 S_B_DDR3_DQM1
4 5
RM147 RM147 0 OHM 0 OHM
S_B_DDR3_DQM0 S_B_DDR3_DQM0
1 8
S_B_DDR3_DQ3 S_B_DDR3_DQ3
2 7
S_B_DDR3_DQ1 S_B_DDR3_DQ1
3 6
S_B_DDR3_DQ7 S_B_DDR3_DQ7
4 5
RM148 RM148 0 OHM 0 OHM
S_B_DDR3_DQ0 S_B_DDR3_DQ0
1 8
S_B_DDR3_DQ2 S_B_DDR3_DQ2
2 7
S_B_DDR3_DQ6 S_B_DDR3_DQ6
3 6
S_B_DDR3_DQ4 S_B_DDR3_DQ4
4 5
S_B_DDR3_DQ13 S_B_DDR3_DQ13
0 Ohm 0 Ohm
1 2
S_B_DDR3_DQ5 S_B_DDR3_DQ5
0 Ohm 0 Ohm
1 2
Adding 0[ohm] Resistor
M_B_DDR3_DQS1 M_B_DDR3_DQS1
110 127
M_B_DDR3_DQS0 M_B_DDR3_DQS0
110 127
110
110
M_B_DDR3_DQSB1 M_B_DDR3_DQSB1
127
M_B_DDR3_DQSB0 M_B_DDR3_DQSB0
127
110
110
110
110
110
110
110
110
M_B_DDR3_MCLKZ M_B_DDR3_MCLKZ
110 127
M_B_DDR3_MCLK M_B_DDR3_MCLK
110 127
110
110
110
110
110
110
S_B_DDR3_DQS1 S_B_DDR3_DQS1
R1286 R1286 0 Ohm 0 Ohm
1 2
S_B_DDR3_DQS0 S_B_DDR3_DQS0
R1287 R1287 0 Ohm 0 Ohm
1 2
S_B_DDR3_DQSB1 S_B_DDR3_DQSB1
R1288 R1288 0 Ohm 0 Ohm
1 2
S_B_DDR3_DQSB0 S_B_DDR3_DQSB0
R1289 R1289 0 Ohm 0 Ohm
1 2
R1290 R1290 R1291 R1291
56 OHM 56 OHM 56 OHM 56 OHM
NC NC NC NC
S I
G
1 9
9 8
8
C1299 C1299
0.01UF/25V 0.01UF/25V
NC NC
S I
G
1 9
9 8
7
MAIN BOARD MAIN BOARD MAIN BOARD
Size Size Size Project Name Project Name Project Name
EU Lv.2 EU Lv.2 EU Lv.2
A4 A4 A4
Date: Date: Date: Tuesday, January 29, 2013 Tuesday, January 29, 2013 Tuesday, January 29, 2013
110
110
110
110
Title : Title : Title :
128. DDR3 B Resistors 128. DDR3 B Resistors 128. DDR3 B Resistors
Engineer: Engineer: Engineer:
CVP DM HW CVP DM HW CVP DM HW
Rev Rev Rev
1.00 1.00 1.00
Sheet Sheet Sheet 128 128 128 of of of 76 76 76