Toshiba 40L7363RK Service Manual page 37

IC100J IC100J
110. MSD8881CV (DDR3)
M_A_DDR3_DQ31 M_A_DDR3_DQ31
E26
125
A_DDR3_DQ31 A_DDR3_DQ31
M_A_DDR3_DQ30 M_A_DDR3_DQ30
E22
125
S I G 1 7 4 5 1 A_DDR3_DQ30 A_DDR3_DQ30
M_A_DDR3_DQ29 M_A_DDR3_DQ29
125 E27
S I G 1 7 4 5 2 A_DDR3_DQ29 A_DDR3_DQ29
M_A_DDR3_DQ28 M_A_DDR3_DQ28
125 E23
S I G 1 7 4 5 3 A_DDR3_DQ28 A_DDR3_DQ28
M_A_DDR3_DQ27 M_A_DDR3_DQ27
D27
125
S I G 1 7 4 5 4
A_DDR3_DQ27 A_DDR3_DQ27
M_A_DDR3_DQ26 M_A_DDR3_DQ26
E21
125
S I G 1 7 4 5 5
A_DDR3_DQ26 A_DDR3_DQ26
M_A_DDR3_DQ25 M_A_DDR3_DQ25
D26
125
S I G 1 7 4 5 7 A_DDR3_DQ25 A_DDR3_DQ25
M_A_DDR3_DQ24 M_A_DDR3_DQ24
D23
125
S I G 1 7 4 5 6 A_DDR3_DQ24 A_DDR3_DQ24
M_A_DDR3_DQ23 M_A_DDR3_DQ23
125 A26
S I G 1 7 4 5 8 A_DDR3_DQ23 A_DDR3_DQ23
M_A_DDR3_DQ22 M_A_DDR3_DQ22
C27
125
S I G 1 7 4 5 9 A_DDR3_DQ22 A_DDR3_DQ22
M_A_DDR3_DQ21 M_A_DDR3_DQ21
C24
125
S I G 1 7 4 6 0 A_DDR3_DQ21 A_DDR3_DQ21
M_A_DDR3_DQ20 M_A_DDR3_DQ20
C28
125
S I G 1 7 4 6 1
A_DDR3_DQ20 A_DDR3_DQ20
M_A_DDR3_DQ19 M_A_DDR3_DQ19
C25
125
S I G 1 7 4 6 2 A_DDR3_DQ19 A_DDR3_DQ19
M_A_DDR3_DQ18 M_A_DDR3_DQ18
B28
125
S I G 1 7 4 6 3 A_DDR3_DQ18 A_DDR3_DQ18
M_A_DDR3_DQ17 M_A_DDR3_DQ17
125 B26
S I G 1 7 4 6 4 A_DDR3_DQ17 A_DDR3_DQ17
M_A_DDR3_DQ16 M_A_DDR3_DQ16
B27
125
S I G 1 7 4 6 5 A_DDR3_DQ16 A_DDR3_DQ16
M_A_DDR3_DQ15 M_A_DDR3_DQ15
F20
125
S I G 1 7 4 6 6 A_DDR3_DQ15 A_DDR3_DQ15
M_A_DDR3_DQ14 M_A_DDR3_DQ14
D18
125
S I G 1 7 4 6 7 A_DDR3_DQ14 A_DDR3_DQ14
M_A_DDR3_DQ13 M_A_DDR3_DQ13
125 D21
S I G 1 7 4 6 8 A_DDR3_DQ13 A_DDR3_DQ13
M_A_DDR3_DQ12 M_A_DDR3_DQ12
F18
125
S I G 1 7 4 6 9 A_DDR3_DQ12 A_DDR3_DQ12
M_A_DDR3_DQ11 M_A_DDR3_DQ11
E20
125
S I G 1 7 4 7 0
A_DDR3_DQ11 A_DDR3_DQ11
M_A_DDR3_DQ10 M_A_DDR3_DQ10
F17
125
S I G 1 7 4 7 1
A_DDR3_DQ10 A_DDR3_DQ10
M_A_DDR3_DQ9 M_A_DDR3_DQ9
D19
125
S I G 1 7 4 7 2 A_DDR3_DQ9 A_DDR3_DQ9
M_A_DDR3_DQ8 M_A_DDR3_DQ8
125 E18
S I G 1 7 4 7 3 A_DDR3_DQ8 A_DDR3_DQ8
M_A_DDR3_DQ7 M_A_DDR3_DQ7
125 C21
S I G 1 7 4 7 4 A_DDR3_DQ7 A_DDR3_DQ7
M_A_DDR3_DQ6 M_A_DDR3_DQ6
C23
125
S I G 1 7 4 7 5
A_DDR3_DQ6 A_DDR3_DQ6
M_A_DDR3_DQ5 M_A_DDR3_DQ5
B20
125
S I G 1 7 4 7 6
A_DDR3_DQ5 A_DDR3_DQ5
M_A_DDR3_DQ4 M_A_DDR3_DQ4
A24
125
S I G 1 7 4 7 7 A_DDR3_DQ4 A_DDR3_DQ4
M_A_DDR3_DQ3 M_A_DDR3_DQ3
C20
125
S I G 1 7 4 7 8 A_DDR3_DQ3 A_DDR3_DQ3
M_A_DDR3_DQ2 M_A_DDR3_DQ2
125 A23
S I G 1 7 4 7 9 A_DDR3_DQ2 A_DDR3_DQ2
M_A_DDR3_DQ1 M_A_DDR3_DQ1
B21
125
S I G 1 7 4 8 0 A_DDR3_DQ1 A_DDR3_DQ1
M_A_DDR3_DQ0 M_A_DDR3_DQ0
B23
125
S I G 1 7 4 5 0
A_DDR3_DQ0 A_DDR3_DQ0
M_A_DDR3_DQS3 M_A_DDR3_DQS3
E24
125
A_DDR3_DQS3 A_DDR3_DQS3
M_A_DDR3_DQS2 M_A_DDR3_DQS2
A27
125
A_DDR3_DQS2 A_DDR3_DQS2
M_A_DDR3_DQS1 M_A_DDR3_DQS1
F19
125
A_DDR3_DQS1 A_DDR3_DQS1
M_A_DDR3_DQS0 M_A_DDR3_DQS0
125 C22
A_DDR3_DQS0 A_DDR3_DQS0
M_A_DDR3_DQSB3 M_A_DDR3_DQSB3
D24
125
A_DDR3_DQSB3 A_DDR3_DQSB3
M_A_DDR3_DQSB2 M_A_DDR3_DQSB2
C26
125
A_DDR3_DQSB2 A_DDR3_DQSB2
M_A_DDR3_DQSB1 M_A_DDR3_DQSB1
G19
125
A_DDR3_DQSB1 A_DDR3_DQSB1
M_A_DDR3_DQSB0 M_A_DDR3_DQSB0
B22
125
A_DDR3_DQSB0 A_DDR3_DQSB0
M_A_DDR3_ODT M_A_DDR3_ODT
E17
125
A_DDR3_ODT A_DDR3_ODT
M_A_DDR3_RESET M_A_DDR3_RESET
125 129 D12
A_DDR3_RESET A_DDR3_RESET
MSD8881CV MSD8881CV
MSTAR/MSD8881CV-W9N MSTAR/MSD8881CV-W9N
[V-U8881CVF] [V-U8881CVF]
10/16 10/16
[DDR-3 INTERFACE 1/2] [DDR-3 INTERFACE 1/2]
M_A_DDR3_A14 M_A_DDR3_A14
B15
A_DDR3_A14 A_DDR3_A14
M_A_DDR3_A13 M_A_DDR3_A13
E11
A_DDR3_A13 A_DDR3_A13 S I G 1 7 4 8 1
M_A_DDR3_A12 M_A_DDR3_A12
F15
S I G 1 7 4 8 2
A_DDR3_A12 A_DDR3_A12
M_A_DDR3_A11 M_A_DDR3_A11
B16
A_DDR3_A11 A_DDR3_A11 S I G 1 7 4 8 3
M_A_DDR3_A10 M_A_DDR3_A10
B18
A_DDR3_A10 A_DDR3_A10 S I G 1 7 4 8 4
M_A_DDR3_A9 M_A_DDR3_A9
E12
A_DDR3_A9 A_DDR3_A9 S I G 1 7 4 8 5
M_A_DDR3_A8 M_A_DDR3_A8
C15
A_DDR3_A8 A_DDR3_A8 S I G 1 7 4 8 6
M_A_DDR3_A7 M_A_DDR3_A7
F12
A_DDR3_A7 A_DDR3_A7 S I G 1 7 4 8 7
M_A_DDR3_A6 M_A_DDR3_A6
C16
S I G 1 7 4 8 8
A_DDR3_A6 A_DDR3_A6
M_A_DDR3_A5 M_A_DDR3_A5
F14
A_DDR3_A5 A_DDR3_A5 S I G 1 7 4 8 9
M_A_DDR3_A4 M_A_DDR3_A4
A17
A_DDR3_A4 A_DDR3_A4 S I G 1 7 4 9 0
M_A_DDR3_A3 M_A_DDR3_A3
D14
S I G 1 7 4 9 1
A_DDR3_A3 A_DDR3_A3
M_A_DDR3_A2 M_A_DDR3_A2
F13
A_DDR3_A2 A_DDR3_A2 S I G 1 7 4 9 2
M_A_DDR3_A1 M_A_DDR3_A1
B17
A_DDR3_A1 A_DDR3_A1 S I G 1 7 4 9 3
M_A_DDR3_A0 M_A_DDR3_A0
E13
S I G 1 7 4 9 4
A_DDR3_A0 A_DDR3_A0
M_A_DDR3_DQM3 M_A_DDR3_DQM3
E25
A_DDR3_DQM3 A_DDR3_DQM3
M_A_DDR3_DQM2 M_A_DDR3_DQM2
B25
A_DDR3_DQM2 A_DDR3_DQM2
M_A_DDR3_DQM1 M_A_DDR3_DQM1
E19
A_DDR3_DQM1 A_DDR3_DQM1
M_A_DDR3_DQM0 M_A_DDR3_DQM0
A20
A_DDR3_DQM0 A_DDR3_DQM0
M_A_DDR3_MCLKZ M_A_DDR3_MCLKZ
B19
A_DDR3_MCLKZ A_DDR3_MCLKZ
M_A_DDR3_MCLK M_A_DDR3_MCLK
C19
A_DDR3_MCLK A_DDR3_MCLK
M_A_DDR3_CKE M_A_DDR3_CKE
C18
A_DDR3_CKE A_DDR3_CKE
M_A_DDR3_BA2 M_A_DDR3_BA2
E15
A_DDR3_BA2 A_DDR3_BA2
M_A_DDR3_BA1 M_A_DDR3_BA1
C17
A_DDR3_BA1 A_DDR3_BA1
M_A_DDR3_BA0 M_A_DDR3_BA0
D15
A_DDR3_BA0 A_DDR3_BA0
M_A_DDR3_WEZ M_A_DDR3_WEZ
G15
A_DDR3_WEZ A_DDR3_WEZ
M_A_DDR3_RASZ M_A_DDR3_RASZ
E16
A_DDR3_RASZ A_DDR3_RASZ
M_A_DDR3_CASZ M_A_DDR3_CASZ
F16
A_DDR3_CASZ A_DDR3_CASZ
M_B_DDR3_DQ15 M_B_DDR3_DQ15
R24
125 127
M_B_DDR3_DQ14 M_B_DDR3_DQ14
125 127 T22
M_B_DDR3_DQ13 M_B_DDR3_DQ13
N25
125 127
M_B_DDR3_DQ12 M_B_DDR3_DQ12
T23
125 127
M_B_DDR3_DQ11 M_B_DDR3_DQ11
125 127 R23
M_B_DDR3_DQ10 M_B_DDR3_DQ10
U23
125 127
M_B_DDR3_DQ9 M_B_DDR3_DQ9
T24
125 127
M_B_DDR3_DQ8 M_B_DDR3_DQ8
125 127 U24
125
M_B_DDR3_DQ7 M_B_DDR3_DQ7
M27
125 127
M_B_DDR3_DQ6 M_B_DDR3_DQ6
125 127 P27
M_B_DDR3_DQ5 M_B_DDR3_DQ5
K27
125 127
M_B_DDR3_DQ4 M_B_DDR3_DQ4
P26
125 127
M_B_DDR3_DQ3 M_B_DDR3_DQ3
125 127 L27
M_B_DDR3_DQ2 M_B_DDR3_DQ2
N26
125 127
M_B_DDR3_DQ1 M_B_DDR3_DQ1
L26
127
M_B_DDR3_DQ0 M_B_DDR3_DQ0
N27
127
125
125
125
125
M_B_DDR3_DQS1 M_B_DDR3_DQS1
T25
125 127
M_B_DDR3_DQS0 M_B_DDR3_DQS0
M26
125 127
M_B_DDR3_DQSB1 M_B_DDR3_DQSB1
R25
125 127
M_B_DDR3_DQSB0 M_B_DDR3_DQSB0
M28
127
125
M_B_DDR3_ODT M_B_DDR3_ODT
P24
125 127
125
M_B_DDR3_RESET M_B_DDR3_RESET
127 G25
125
125
125
IC100K IC100K
[V-U8881CVF] [V-U8881CVF]
11/16 11/16
[DDR-3 INTERFACE 2/2] [DDR-3 INTERFACE 2/2]
E28
B_DDR3_DQ15 B_DDR3_DQ15 B_DDR3_A14 B_DDR3_A14
H25
B_DDR3_DQ14 B_DDR3_DQ14 B_DDR3_A13 B_DDR3_A13
M23
B_DDR3_DQ13 B_DDR3_DQ13 B_DDR3_A12 B_DDR3_A12
F28
B_DDR3_DQ12 B_DDR3_DQ12 B_DDR3_A11 B_DDR3_A11
H26
B_DDR3_DQ11 B_DDR3_DQ11 B_DDR3_A10 B_DDR3_A10
G24
B_DDR3_DQ10 B_DDR3_DQ10 B_DDR3_A9 B_DDR3_A9
F27
B_DDR3_DQ9 B_DDR3_DQ9 B_DDR3_A8 B_DDR3_A8
J23
B_DDR3_DQ8 B_DDR3_DQ8 B_DDR3_A7 B_DDR3_A7
F26
B_DDR3_A6 B_DDR3_A6
J24
B_DDR3_DQ7 B_DDR3_DQ7 B_DDR3_A5 B_DDR3_A5
G26
B_DDR3_DQ6 B_DDR3_DQ6 B_DDR3_A4 B_DDR3_A4
K25
B_DDR3_DQ5 B_DDR3_DQ5 B_DDR3_A3 B_DDR3_A3
K23
B_DDR3_DQ4 B_DDR3_DQ4 B_DDR3_A2 B_DDR3_A2
G27
B_DDR3_DQ3 B_DDR3_DQ3 B_DDR3_A1 B_DDR3_A1
J25
B_DDR3_DQ2 B_DDR3_DQ2 B_DDR3_A0 B_DDR3_A0
B_DDR3_DQ1 B_DDR3_DQ1
B_DDR3_DQ0 B_DDR3_DQ0
P23
B_DDR3_DQM1 B_DDR3_DQM1
K26
B_DDR3_DQM0 B_DDR3_DQM0
J28
B_DDR3_DQS1 B_DDR3_DQS1 B_DDR3_MCLKZ B_DDR3_MCLKZ
J26
B_DDR3_DQS0 B_DDR3_DQS0 B_DDR3_MCLK B_DDR3_MCLK
J27
B_DDR3_DQSB1 B_DDR3_DQSB1 B_DDR3_CKE B_DDR3_CKE
B_DDR3_DQSB0 B_DDR3_DQSB0
L24
B_DDR3_BA2 B_DDR3_BA2
H27
B_DDR3_ODT B_DDR3_ODT B_DDR3_BA1 B_DDR3_BA1
L23
B_DDR3_BA0 B_DDR3_BA0
B_DDR3_RESET B_DDR3_RESET
N23
B_DDR3_WEZ B_DDR3_WEZ
M25
B_DDR3_RASZ B_DDR3_RASZ
M24
B_DDR3_CASZ B_DDR3_CASZ
MSD8881CV MSD8881CV
MSTAR/MSD8881CV-W9N MSTAR/MSD8881CV-W9N
MAIN BOARD MAIN BOARD MAIN BOARD
Size Size Size Project Name Project Name Project Name
EU Lv.2 EU Lv.2 EU Lv.2
Custom Custom Custom
Date: Date: Date: Tuesday, January 29, 2013 Tuesday, January 29, 2013 Tuesday, January 29, 2013
M_B_DDR3_A14 M_B_DDR3_A14
127
M_B_DDR3_A13 M_B_DDR3_A13
127
M_B_DDR3_A12 M_B_DDR3_A12
127
M_B_DDR3_A11 M_B_DDR3_A11
127
M_B_DDR3_A10 M_B_DDR3_A10
127
M_B_DDR3_A9 M_B_DDR3_A9
127
M_B_DDR3_A8 M_B_DDR3_A8
127
M_B_DDR3_A7 M_B_DDR3_A7
127
M_B_DDR3_A6 M_B_DDR3_A6
127
M_B_DDR3_A5 M_B_DDR3_A5
127
M_B_DDR3_A4 M_B_DDR3_A4
127
M_B_DDR3_A3 M_B_DDR3_A3
127
M_B_DDR3_A2 M_B_DDR3_A2
127
M_B_DDR3_A1 M_B_DDR3_A1
127
M_B_DDR3_A0 M_B_DDR3_A0
127
M_B_DDR3_DQM1 M_B_DDR3_DQM1
127
M_B_DDR3_DQM0 M_B_DDR3_DQM0
127
M_B_DDR3_MCLKZ M_B_DDR3_MCLKZ
127 129
M_B_DDR3_MCLK M_B_DDR3_MCLK
127 129
M_B_DDR3_CKE M_B_DDR3_CKE
127
M_B_DDR3_BA2 M_B_DDR3_BA2
127
M_B_DDR3_BA1 M_B_DDR3_BA1
127
M_B_DDR3_BA0 M_B_DDR3_BA0
127
M_B_DDR3_WEZ M_B_DDR3_WEZ
127
M_B_DDR3_RASZ M_B_DDR3_RASZ
127
M_B_DDR3_CASZ M_B_DDR3_CASZ
127
Title : Title : Title :
110. MSD8881CV (DDR3) 110. MSD8881CV (DDR3) 110. MSD8881CV (DDR3)
Engineer: Engineer: Engineer:
CVP DM HW CVP DM HW CVP DM HW
Rev Rev Rev
1.00 1.00 1.00
Sheet Sheet Sheet 110 110 110 of of of 76 76 76