Toshiba 40L7363RK Service Manual page 45

126. DDR3 A Resistors
Adding 0[ohm] Resistor
RM120 RM120 0 OHM 0 OHM
M_A_DDR3_DQ29 M_A_DDR3_DQ29
1
110
S I G 1 7 4 5 2
M_A_DDR3_DQ27 M_A_DDR3_DQ27
2
110
S I G 1 7 4 5 4
M_A_DDR3_DQ31 M_A_DDR3_DQ31
3
110
M_A_DDR3_DQ25 M_A_DDR3_DQ25
4
110
S I G 1 7 4 5 7
RM121 RM121 0 OHM 0 OHM
M_A_DDR3_DQ28 M_A_DDR3_DQ28
1
110
S I G 1 7 4 5 3
M_A_DDR3_DQ24 M_A_DDR3_DQ24
2
110
S I G 1 7 4 5 6
M_A_DDR3_DQ30 M_A_DDR3_DQ30
3
110
S I G 1 7 4 5 1
M_A_DDR3_DQ26 M_A_DDR3_DQ26
4
110
S I G 1 7 4 5 5
RM122 RM122 0 OHM 0 OHM
M_A_DDR3_DQ16 M_A_DDR3_DQ16
1
110
S I G 1 7 4 6 5
M_A_DDR3_DQ18 M_A_DDR3_DQ18
2
110
S I G 1 7 4 6 3
M_A_DDR3_DQ22 M_A_DDR3_DQ22
3
110
S I G 1 7 4 5 9
M_A_DDR3_DQ20 M_A_DDR3_DQ20
4
110
S I G 1 7 4 6 1
RM123 RM123 0 OHM 0 OHM
M_A_DDR3_DQM2 M_A_DDR3_DQM2
1
110
M_A_DDR3_DQ19 M_A_DDR3_DQ19
2
110
S I G 1 7 4 6 2
M_A_DDR3_DQ17 M_A_DDR3_DQ17
3
110
S I G 1 7 4 6 4
M_A_DDR3_DQ23 M_A_DDR3_DQ23
4
110
S I G 1 7 4 5 8
RM124 RM124 0 OHM 0 OHM
M_A_DDR3_DQ13 M_A_DDR3_DQ13
1
110
S I G 1 7 4 6 8
M_A_DDR3_DQ11 M_A_DDR3_DQ11
2
110
S I G 1 7 4 7 0
M_A_DDR3_DQ15 M_A_DDR3_DQ15
3
110
S I G 1 7 4 6 6
M_A_DDR3_DQ9 M_A_DDR3_DQ9
4
110
S I G 1 7 4 7 2
RM125 RM125 0 OHM 0 OHM
M_A_DDR3_DQ12 M_A_DDR3_DQ12
1
110
S I G 1 7 4 6 9
M_A_DDR3_DQ8 M_A_DDR3_DQ8
2
110
S I G 1 7 4 7 3
M_A_DDR3_DQ14 M_A_DDR3_DQ14
3
110
S I G 1 7 4 6 7
M_A_DDR3_DQ10 M_A_DDR3_DQ10
4
110
S I G 1 7 4 7 1
RM126 RM126 0 OHM 0 OHM
M_A_DDR3_DQM0 M_A_DDR3_DQM0
1
110
M_A_DDR3_DQ3 M_A_DDR3_DQ3
2
110
S I G 1 7 4 7 8
M_A_DDR3_DQ1 M_A_DDR3_DQ1
3
110
S I G 1 7 4 8 0
M_A_DDR3_DQ7 M_A_DDR3_DQ7
4
110
S I G 1 7 4 7 4
RM128 RM128 0 OHM 0 OHM
M_A_DDR3_DQ0 M_A_DDR3_DQ0
1
110
S I G 1 7 4 5 0
M_A_DDR3_DQ2 M_A_DDR3_DQ2
2
110
S I G 1 7 4 7 9
M_A_DDR3_DQ6 M_A_DDR3_DQ6
3
110
S I G 1 7 4 7 5
M_A_DDR3_DQ4 M_A_DDR3_DQ4
4
110
S I G 1 7 4 7 7
M_A_DDR3_DQM3 M_A_DDR3_DQM3
R1250 R1250 0 Ohm 0 Ohm
1
110
M_A_DDR3_DQ21 M_A_DDR3_DQ21
R1251 R1251 0 Ohm 0 Ohm
1
110
S I G 1 7 4 6 0
M_A_DDR3_DQM1 M_A_DDR3_DQM1
R1252 R1252 0 Ohm 0 Ohm
1
110
M_A_DDR3_DQ5 M_A_DDR3_DQ5
R1253 R1253 0 Ohm 0 Ohm
1
110
S I G 1 7 4 7 6
S_A_DDR3_DQ29 S_A_DDR3_DQ29
8
125
S_A_DDR3_DQ27 S_A_DDR3_DQ27
7
125
S_A_DDR3_DQ31 S_A_DDR3_DQ31
6
125
S_A_DDR3_DQ25 S_A_DDR3_DQ25
5
125
S_A_DDR3_DQ28 S_A_DDR3_DQ28
8
125
S_A_DDR3_DQ24 S_A_DDR3_DQ24
7
125
S_A_DDR3_DQ30 S_A_DDR3_DQ30
6
125
S_A_DDR3_DQ26 S_A_DDR3_DQ26
5
125
S_A_DDR3_DQ16 S_A_DDR3_DQ16
8
125
S_A_DDR3_DQ18 S_A_DDR3_DQ18
7
125
S_A_DDR3_DQ22 S_A_DDR3_DQ22
6
125
S_A_DDR3_DQ20 S_A_DDR3_DQ20
5
125
S_A_DDR3_DQM2 S_A_DDR3_DQM2
8
125
S_A_DDR3_DQ19 S_A_DDR3_DQ19
7
125
S_A_DDR3_DQ17 S_A_DDR3_DQ17
6
125
S_A_DDR3_DQ23 S_A_DDR3_DQ23
5
125
S_A_DDR3_DQ13 S_A_DDR3_DQ13
8
125
S_A_DDR3_DQ11 S_A_DDR3_DQ11
7
125
S_A_DDR3_DQ15 S_A_DDR3_DQ15
6
125
S_A_DDR3_DQ9 S_A_DDR3_DQ9
5
125
S_A_DDR3_DQ12 S_A_DDR3_DQ12
8
125
S_A_DDR3_DQ8 S_A_DDR3_DQ8
7
125
S_A_DDR3_DQ14 S_A_DDR3_DQ14
6
125
S_A_DDR3_DQ10 S_A_DDR3_DQ10
5
125
S_A_DDR3_DQM0 S_A_DDR3_DQM0
8
125
S_A_DDR3_DQ3 S_A_DDR3_DQ3
7
125
S_A_DDR3_DQ1 S_A_DDR3_DQ1
6
125
S_A_DDR3_DQ7 S_A_DDR3_DQ7
5
125
S_A_DDR3_DQ0 S_A_DDR3_DQ0
8
125
S_A_DDR3_DQ2 S_A_DDR3_DQ2
7
125
S_A_DDR3_DQ6 S_A_DDR3_DQ6
6
125
S_A_DDR3_DQ4 S_A_DDR3_DQ4
5
125
S_A_DDR3_DQM3 S_A_DDR3_DQM3
2
125
S_A_DDR3_DQ21 S_A_DDR3_DQ21
2
125
S_A_DDR3_DQM1 S_A_DDR3_DQM1
2
125
S_A_DDR3_DQ5 S_A_DDR3_DQ5
2
125
Adding 0[ohm] Resistor
M_A_DDR3_DQS3 M_A_DDR3_DQS3
R1254 R1254 0 Ohm 0 Ohm
1 2
110
M_A_DDR3_DQS2 M_A_DDR3_DQS2
R1255 R1255 0 Ohm 0 Ohm
1 2
110
M_A_DDR3_DQS1 M_A_DDR3_DQS1
R1256 R1256 0 Ohm 0 Ohm
1 2
110
M_A_DDR3_DQS0 M_A_DDR3_DQS0
R1257 R1257 0 Ohm 0 Ohm
1 2
110
M_A_DDR3_DQSB3 M_A_DDR3_DQSB3
R1258 R1258 0 Ohm 0 Ohm
1 2
110
M_A_DDR3_DQSB2 M_A_DDR3_DQSB2
R1259 R1259 0 Ohm 0 Ohm
1 2
110
M_A_DDR3_DQSB1 M_A_DDR3_DQSB1
R1260 R1260 0 Ohm 0 Ohm
1 2
110
M_A_DDR3_DQSB0 M_A_DDR3_DQSB0
R1261 R1261 0 Ohm 0 Ohm
1 2
110
S_A_DDR3_DQS3 S_A_DDR3_DQS3
125
S_A_DDR3_DQS2 S_A_DDR3_DQS2
125
S_A_DDR3_DQS1 S_A_DDR3_DQS1
125
S_A_DDR3_DQS0 S_A_DDR3_DQS0
125
S_A_DDR3_DQSB3 S_A_DDR3_DQSB3
125
S_A_DDR3_DQSB2 S_A_DDR3_DQSB2
125
S_A_DDR3_DQSB1 S_A_DDR3_DQSB1
125
S_A_DDR3_DQSB0 S_A_DDR3_DQSB0
125
Title : Title : Title :
Engineer: Engineer: Engineer:
MAIN BOARD MAIN BOARD MAIN BOARD
Size Size Size Project Name Project Name Project Name
EU Lv.2 EU Lv.2 EU Lv.2
A4 A4 A4
Date: Date: Date: Tuesday, January 29, 2013 Tuesday, January 29, 2013 Tuesday, January 29, 2013 Sheet Sheet Sheet
126. DDR3 A Resistors 126. DDR3 A Resistors 126. DDR3 A Resistors
CVP DM HW CVP DM HW CVP DM HW
Rev Rev Rev
1.00 1.00 1.00
126 126 126 of of of 76 76 76