Panasonic KX-FT932RU-B Service Manual page 17

6.3.2. Flash Memory (IC2)
This 512KB ROM (FLASH MEMORY) carries a common area of 32KB and bank areas which each have 8KB (BK4~BK63). The
addresses from 0000H to 7FFFH are for the common area and from 8000H to 9FFFH are for the bank areas.
6.3.3. Dynamic RAM (IC4)
The DRAM serves as CPU and receives memory.
The address is F200H~F3FFH (DRAM access window 1) and F600H~F7FFH (DRAM access window 2).
6.3.4. Reset Circuit (Watch dog timer)
The output signal (reset) from pin 4 of the voltage detect IC (IC3) is input to the ASIC (IC1) 114 pin.
1. During a momentary power interruption, a positive reset pulse of 50~70 msec is generated and the system is reset com-
pletely.
2. The watch dog timer, built-in the ASIC (IC1), is initialized by the CPU about every 1.5 ms.
When a watch dog error occurs, pin 115 of the ASIC (IC1) becomes low level.
The terminal of the 'WDERR' signal is connected to the reset line, so the 'WDERR' signal works as the reset signal.
KX-FT932RU-B/KX-FT932CA-B/KX-FT932UA-B/KX-FT934RU-B/KX-FT934CA-B/KX-FT934UA-B
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