General Features - LG KM500 Service Manual

3. HW Circuit Description

• General features

ARM946E-S CPU core (16KB instruction/data cache, operating up to 200MHz)
8K bytes of internal boot ROM with various boot procedure (NAND, USB, EHI) and security
64K bytes of internal SRAM for general usage
USB2.0 Device (high, full speed)
I2S interface for external audio
I2C compatible serial bus for audio CODEC & CCD/CMOS sensor control
32-bit 1Hz counter
RTC (Real Time Clock) for battery backup
EHI (External Host Interface) for parallel host interface
Secure Digital Card (SD)
3.4.1 Core
The TCC74x has adopted the ARM946E-S (r1p1) core for controlling system and processing various
kinds of digital signals. The ARM946E-S is a Harvard architecture cached processor with separate
16Kbyte data and 16Kbytes instruction caches, each with 8-word of line length. A protection unit
allows eight regions of memory to be defined, each with individual cache and write buffer
configurations and access permissions. The cache system is software configurable to provide highest
average of performance or to meet the needs of real-time systems.
The followings are key features of the TCC74xx CPU core.
CPU ARM946E-S
Cache 16KB for Data / 16KB for Instruction
TCM 4KB dual port data TCM
3.4.2 USB2.0 Device Controller
The TCC7402 USB2.0 Device supports a fully compliant to USB 2.0 specification, highspeed (480
Mbps) functions and suspend/resume signaling. The USB function controller has an endpoint EP0 for
control, two in/output endpoints EP1/EP2 for bulk data transaction and an EP3 for interrupt data
transaction.
3.4.3 EHI
This LSI has the external host interface (EHI) that allows the external host device to be connected to
the on-chip system bus. The external host device can be directly connected to 68/80-series interfaces
and access the memory area of this LSI. For software based data transfer, EHI can generate the
internal interrupt of this LSI, and this LSI can also send interrupt request to the external host
controller.
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