Onkyo HT-R820THX Service Manual page 47

IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-10
Q701: CS494003CQZ (Multi-Standard Audio Decoder)-4
TERMINAL DESCRIPTION
LRCLK1 - Audio Output Sample Rate Clock
Bidirectional digital-audio output frame clock for AUDATA4, AUDATA5, AUDATA6, and AUDATA7. As an output, LRCLK1 can provide all standard
output sample rates up to 192 kHz and is synchronous to MCLK. As an input, LRCLK1 is independent of MCLK.
BIDIRECTIONAL - Default: INPUT
AUDATA0 - Digital Audio Output 0
PCM digital-audio data output. OUTPUT
AUDATA1 - Digital Audio Output 1
PCM digital-audio data output. OUTPUT
AUDATA2 - Digital Audio Output 2
PCM digital-audio data output. OUTPUT
AUDATA3, XMT958A - Digital Audio Output 3, S/PDIF Transmitter
CMOS level output that outputs a biphase-mark encoded (S/PDIF) IEC60958 signal or digital audio data which is capable of carrying two channels of
PCM digital audio. OUTPUT
AUDATA4, GPIO28 - Digital Audio Output 4, General Purpose I/O
PCM digital-audio data output. This pin can act as a general-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: OUTPUT
AUDATA5, GPIO29 - Digital Audio Output 5, General Purpose I/O
PCM digital-audio data output. This pin can act as a general-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: OUTPUT
AUDATA6, GPIO30 - Digital Audio Output 6, General Purpose I/O
PCM digital-audio data output. This pin can act as a general-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: OUTPUT
AUDATA7, XMT958B, GPIO3 - Digital Audio Output 7, S/PDIF Transmitter, General Purpose I/O
CMOS level output that contains a biphase-mark encoded (S/PDIF) IEC60958 signal or digital audio data which is capable of carrying two channels
of PCM digital audio. This pin can also act as a general-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: OUTPUT
DBCK - Debug Clock
Must be tied high to 3.3k ohm resistor. INPUT
DBDA - Debug Data
Must be tied high to 3.3k ohm resistor. BIDIRECTIONAL - Default: INPUT
SLCKN, GPIO22 - PCM Audio Input Bit Clock, General Purpose I/O
Digital-audio bit clock that is an input. SCLKN operates asynchronously from all other DSPAB clocks. The active edge of SCLKN can be programmed
by the DSP. This pin can act as a eneral-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: INPUT
LRCLKN, GPIO23 - PCM Audio Input Sample Rate Clock, General Purpose I/O
Digital-audio frame clock input. LRCLKN operates asynchronously from all other DSPAB clocks. The polarity of LRCLKN for a particular subframe
can be programmed by the DSP. This pin can act as a general-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: INPUT
SDATAN0, GPIO24 - PCM Audio Input Data, General Purpose I/O
Digital-audio PCM data input. This pin can act as a general-purpose input or output that can be individually configured and controlled by DSPC.
BIDIRECTIONAL - Default: INPUT
TX-SR502/E/8250/HT-R520