Onkyo HT-R820THX Service Manual page 46

IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-9
Q701: CS494003CQZ (Multi-Standard Audio Decoder)-3
TERMINAL DESCRIPTION
FLRCLKN1 - PCM Audio Input Sample Rate Clock
Digital-audio frame clock input. FLRCLKN1 typically is run at the sampling frequency. FLRCLKN1 operates asynchronously from all other DSPAB
clocks. The polarity of FLRCLKN1 for a particular subframe can be programmed by the DSP.
BIDIRECTIONAL - Default: INPUT
FSDATAN1 - PCM Audio Data Input One
Digital-audio data input that can accept from one compressed line or 2 channels of PCM data. FSDATAN1 can be sampled with either edge of
FSCLKN1, depending on how FSCLKN1 has been configured. INPUT
CMPCLK, FSCLKN2 - PCM Audio Input Bit Clock
Digital-audio bit clock input. FSCLKN2 operates asynchronously from all other DSPAB clocks. The active edge of FSCLKN2 can be programmed
by the DSP.
BIDIRECTIONAL - Default: INPUT
CMPDAT, FSDATAN2 - PCM Audio Data Input Number Two
Digital-audio data input that can accept either one compressed line or 2 channels of PCM data. FSDATAN2 can be sampled with either edge of
FSCLKN2, depending on how FSCLKN2 has been configured.
BIDIRECTIONAL - Default: INPUT
FDBCK - Reserved
This pin is reserved and should be pulled up with an external 3.3k resistor. INPUT
FDBDA - Reserved
This pin is reserved and should be pulled up with an external 3.3k resistor.
BIDIRECTIONAL - Default: INPUT
PLLVDD - PLL Supply Voltage
2.5 V PLL supply.
PLLVSS - PLL Ground Voltage
PLL ground.
RESET - Master Reset Input
Asynchronous active-low master reset input. Reset should be low at power-up to initialize the DSP and to guarantee that the device is not active during
initial power-on stabilization periods. At the rising edge of reset the host interface mode of DSPAB is selected contingent on the state of the FHS0,
FHS1, and FHS2 pins. At the rising edge of reset the host interface mode of DSPC is selected contingent on the state of the UHSO, UHS1, and
UHS2 pins. If reset is low all bidirectional pins are high-Z inputs. INPUT
TEST - Reserved
This should be tied low for normal operation. INPUT
MCLK - Audio Master Clock
Bidirectional master audio clock. As an output, MCLK provides a low jitter oversampling clock.
MCLK supports all standard oversampling frequencies. BIDIRECTIONAL - Default: INPUT
SCLK0 - Audio Output Bit Clock
Bidirectional digital-audio output bit clock for AUDATA0, AUDATA1, AUDATA2, and AUDATA3.
As an output, SCLK0 can provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs frequencies and is synchronous to MCLK. As an input, SCLK0 is independent
of MCLK.
BIDIRECTIONAL - Default: INPUT
SCLK1 - Audio Output Bit Clock
Bidirectional digital-audio output bit clock for AUDATA4, AUDATA5, AUDATA6, and AUDATA7.
As an output, SCLK1 can provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs frequencies and is synchronous to MCLK. As an input, SCLK1 is independent
of MCLK.
BIDIRECTIONAL - Default: INPUT
LRCLK0 - Audio Output Sample Rate Clock
Bidirectional digital-audio output frame clock for AUDATA0, AUDATA1, AUDATA2, and AUDATA3. As an output, LRCLK0 can provide all standard
output sample rates up to 192 kHz and is synchronous to MCLK. As an input, LRCLK0 is independent of MCLK.
BIDIRECTIONAL - Default: INPUT
TX-SR502/E/8250/HT-R520