Circuit Diagram - LG -A100 Service Manual

7. CIRCUIT DIAGRAM

TP101
F_MODE
UART_TX TP102
UART_RX
TP103
VAUX_2V85
10K
R125
DNI
R126
VDD_IO_1V8
R112
R114
LGE Internal Use Only
2-6-1_1_IFX_EGV3_BASIC
VRTC
C102 C101
2.2u 0.1uF
VBAT
VDD_IO_1V8
C103
VSIM_PWR
1u
VDD_IO_1V8
C105
1UF
VPMU
VDDXO VDDTDC VDDTRX VDDRF2 VDDMS VBAT
C123
0.22uF
STAR_GND
DIRTY_GND
J1
KP_0
J2
KEY_OUT1 KP_1
M4
KEY_OUT2 KP_2
L2 CLEAN_GND CLEAN_GND
KEY_OUT3 KP_3
M3
KEY_OUT4 KP_4
K1
KEY_IN0 KP_5
VDDP_DIG1
K2
KEY_IN1 KP_6
K3 DIRTY_GND DIRTY_GNDDIRTY_GND
KEY_IN2 KP_7
L1
KEY_IN3 KP_8
K4
KEY_IN4 KP_9
P14
RXD0 EX4IN
M14
TXD0 VDDP_DIG2
M13
UART_RX RXD1
N13
UART_TX TXD1
N11
SSC0_MTSR
M11
SSC0_MRST
P12 VDDP_DIG3
SSC0_CLK
N12
DISP_RESET
U102
P10
I2C_SCL I2C_SCL
M10
I2C_SDA I2C_SDA
K16
SIM_DATA_1 CC_IO_1
K14
SIM_CLK_1 CC_CLK_1
L15
SIM_RST_1 CC_RST_1 VDDP_SIM
L16
CC_IO_2
K13
CC_CLK_2
M15
CC_RST_2
H1
JTAG_TDO TDO
G1
JTAG_TDI TDI
H2
JTAG_TMS TMS Max. Curr Volt.
G2 VDDP_DIG1
JTAG_TCK TCK
G3
JTAG_TRST_N TRST_N
VDD1V8 450mA 1.8V
G8
TRIG_IN
H6
TRIG_OUT
P15 VCORE 100mA 1.2V
MON1
G7 VDDP_DIG2
MON2
G4 VANA 10mA 1.3V
MON3 VDDP_DIG1
10K H5
MON4
VAUX 150mA 2.85V
DNI N6
MEM_AD_[00] AD0
N5
MEM_AD_[01] AD1 VRTC 2mA 2.3V
P7
VDDP_MEM2
MEM_AD_[02] AD2
N9
MEM_AD_[03] AD3
T10 VSIM 30mA 2.85V
AD4
T11
AD5
T12 VRF1 60mA 1.8V
AD6
R14
AD7
T7 VRF2 70mA 2.5V
MEM_AD_[08] AD8
R7
MEM_AD_[09] AD9
T8
MEM_AD_[10] AD10 VDDMMD 12mA 1.3V
T9
MEM_AD_[11] AD11
R10
MEM_AD_[12] AD12 VDDP_MEM1
R12 VDD_TDC 6mA 1.3V
MEM_AD_[13] AD13
T13
MEM_AD_[14] AD14
T14 VDD_TRX 30mA 1.4V
MEM_AD_[15] AD15
T15
MEM_A_[16] A16
R6 VDD_NEG 100mA -1.3V
A17
T3
A18
T4
A19
R16
A20
R15
A21
T5
A22
VMIC_BIAS_P
VDD_IO_1V8 VAUX_2V85
R106
R105
DNI 0
VCORE
VAUX_2V85 VDD_IO_1V8 VAUX_2V85
A9
FMRIN
TSX-3225 X101
A8
FMRINX 3 4
HOT2 GND2
2 1
GND1 HOT1
F1
XO
26MHz
F2
XOX
A4
RX12 RF_LB_RXP
A3
RX12X RF_LB_RXN
A6
RX34 RF_HB_RXP
A5
RX34X RF_HB_RXN
B1
TX1 RF_LB_TX
B2
TX2 RF_HB_TX
A2
FE1
RF_VLOGIC
C1
FE2
RF_2G_BS
D2
PABS
E3
PAEN RF_TX_EN
X102
D3
PABIAS MC-146_12_5PF
D1
VRAMP RF_TX_RAMP
3
C3 4
VDET
F7
FSYS1
1 2
K5
CLKOUT0
VDDP_DIG1 N4
T2IN NLCD_RESET_1.8 C133 C134 32.768KHz
M16
F32K 22p 22p
VDDP_RTC N16
OSC32K
N15
RESET_OUT_N
N1
RESET_IN_N RESET_IN
M2
EX2IN NMI_N
M1
CC16IOA CC03IO ABB_INT_N
L5
INTR? CC05IO
VDDP_DIG1 N2
DIGUP1 KEY_BACKLIGHT R109
P2
DIGUP2 F_MODE
10K
P1
DIGUP_CLK END_KEY
H14
VRTC ONOFF
R110
D16
CS 100Kohms
E15
CSB
Q101
C16
VCHG
E16 R113
VDDCHG
C15
470ohms
VSHNT
E14
SENSEN VBAT
D15
SENSEP
J14 R115
LEDFBN
J16 VBAT VDD_IO_1V8
3.9K
LEDFBP
J15
LEDDRV
R117
L101 3.3u
G16
39K
SD1SW
H15
R118
SD1_FB
F16
2.4K
VDD_SD1
H16
C135
VSS_SD1
22uF
P16 C136 ECZH0025502
TP108 (22uF,6.3V,20%,X5R,2012)
ADV_N MEM_AVD_N
R2 10u
VDDP_MEM1 WR_N MEM_WR_N
T6
TP109 ECCH0007803
RD_N MEM_RD_N
P5 (10uF,10V,M,X5R,1608)
VDDP_MEM2 WAIT_N
R1
VDDP_MEM1 RDY_N
N8
VDDP_MEM2 BFCLKO MEM_CLK
CLEAN_GND R9
BC0_N
VDDP_MEM1 R8
BC1_N
M6
VDDP_MEM2 CS0_N ROM_CS_N
R3
TP104
CS1_N
VDDP_MEM1 T2
CS3_N LCD_CS_N
- 99 -
Serial Flash
VAUX_2V85
U103
C132 1u
L102 27n
ROM_CS_N 1 8
/CS VCC
L103 27n L105
2 7
MEM_AD_[01] DO_IO1 /HOLD_IO3
L104 27n L106
3 6
MEM_AD_[02] /WP_IO2 CLK
L107
4 5
GND DI_IO0
G_SLUG
9
VDD_IO_1V8
DSS
R116
10K
RESET_IN
JTAG_TDO
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TRST_N
(NOT MOUNTED)
(FOR SW DEBUGGING / NOT MOUNTED)
ON BOARD ARM9 JTAG & ETM INTERFACE
Copyright © 2011 LG Electronics. Inc. All right reserved.
7. CIRCUIT DIAGRAM
27n
MEM_AD_[03]
27n
MEM_CLK
27n
MEM_AD_[00]
CN101
1
2
3
4
5
6
7
8
9
Only for training and service purposes