Lo Phase-Locked Loop - LG L704I Service Manual

3. TECHNICAL BRIEF

3.4 LO Phase-locked Loop

All LO functions are fully integrated on-chip and do not require user any adjustment. QUALCOMM has
established and implemented frequency plans and LO generation schemes that support the radioOne
Platform B-series chipset. Only one area requires handset designer attention: the loop filters relating to
each PLL. These are addressed in this chapter.
All the UMTS Rx, GSM Rx, and GPS PLL circuits are included within the RFICs: reference dividers,
phase detectors, charge pumps, feedback dividers, and digital logic.
There are four integrated VCOs and PLLs within the Platform B (RFCMOS) chipset as shown in Figure
5-1 and Figure 5-2:
■ Figure 5-1
1. PLL1, within the RTR6275 IC, produces the LO for up- and down-conversion of GSM Tx/Rx, and
UMTS Tx.
2. PLL2, within RTR6275 IC, produces the Rx LO for one of the (high band) UMTS receive Paths.
■ Figure 5-2
3. PLL3, within the RFR6275 IC, produces the Rx LO for the remaining UMTS receive paths.
4. PLL4, within the RFR6275 IC, produces the Rx LO for the GPS receive path.
Within the RFICs, a buffered 19.2 MHz TCXO signal provides the synthesizer input (REF), the
frequency reference to which the PLL is phase- and frequency-locked. The reference is divided by the
R-Counters to create a fixed frequency input to the phase detector, FR. The other phase detector input
(FV) varies as the loop acquires lock, and is generated by dividing the VCO frequency using the
feedback path N-Counter. The closed loop will force FV to equal FR when locked. If the loop is not
locked, the error between FV and FR will create an error signal at the output of the charge pump. This
error signal is filtered by the loop filter components and applied to the VCO, tuning the output
frequency so that the error is decreased. Ultimately, the loop forces the error to approach zero and the
PLL is phase- and frequency-locked.
LGE Internal Use Only
RFR6275 PLLs functional block diagram
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Only for training and service purposes