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Pin No.
Pin Name
34
RFM
35
RFTC
36
LD
37
PD
38 ~ 39
PD1 ~ PD2
40
FEBIAS
41 ~ 42
F ~ E
43
EI
44
VEE
45
TEO
46
LPFI
47
TEI
48
ATSC
49
TZC
50
TDFCT
51
VC
TE
L 13942296513
52
FZC
IC, CXD2589Q
Pin No.
Pin Name
1
VSS
2
LMUT
3
RMUT
4
SQCK
5
SQSO
6
SENS
7
DATA
8
XLAT
9
CLOK
10
SEIN1
11
CNIN
12
DATO
www
13
XLTO
14
CLKO
.
15
SEIN2
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I/O
Anti-reverse input terminal for RF summing amplifier. The gain of RF amplifier is decided by the
I
connection resistance between RF-M and RF-O terminals.
I
This is a pin where the selection time constant is externally connected to control the RF level.
O
APC amplifier output terminal.
I
APC amplifier input terminal.
RFI-V amplifier inverted input pin. These pins are connected to the A+C and B+C pins of the
I
optical pickup, receiving by currents input.
I/O
Bias adjustment pin of the focus error amplifier. (Not used)
F and EIV amplifier inverted input pins. These pins are connected to the F and E of the optical
I
pickup, receiving by current input.
Gain adjustment pin of the I-V amplifier E. (When not in use of BAL automatic adjustment)
–
(Not used)
–
GND connection pin.
O
Output terminal for tacking-error amplifier. Output E-F signal.
I
BAL adjustment comparator input pin. (Input through LPF from TEO)
I
Input terminal for tracking error.
I
Window-comparator input terminal for detecting ATSC.
I
Input terminal for tracking-zero cross comparator.
I
Capacitor connection pin for the time constant used when there is defect.
O
Output terminal for DC voltage reduced to half of VCC+VEE.
I
Input terminal for focus-zero cross comparator.
I/O
–
GND.
O
Left channel zero detection flag. (Not used)
O
Right channel zero detection flag. (Not used)
I
SQSO readout clock input.
O
Sub Q 80-bit serial output.
O
SENS output to CPU.
I
Serial data input from CPU.
I
Latch input from CPU. Serial data is latched at the falling edge.
I
Serial data transfer clock input from CPU.
I
SENS input from SSP.
I
Track jump count signal input.
I
Serial data output to SSP.
O
Serial data latch output to SSP. Latched at the falling edge.
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O
Serial data transfer clock output to SSP.
i
I
Microcomputer extended interface (input A). (SENS input from SSP.)
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2 9
8
Description
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3
6 7
1 3
1 5
Description
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.
36
9 4
2 8
0 5
8
2 9
9 4
2 8
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9 9
9 9
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