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Circuit Diagrams and PWB Layouts
SSB v1: MT5335 Video Processor
8
7
MT5335 VIDEO PROCESSOR
B07
F
U203
OSDA0
204
OSDA0
OSCL0
205
OSCL0
OSDA1
63
OSDA1
OSCL1
62
OSCL1
BL_DIM
191
OPWM0
OPWM1
202
OPWM1
OPWM2
203
MTK_IC_RESET
OPWM2
146
VCXO
143
OXTALO
XTALO
OXTALI
144
XTALI
147
AVCC_SRV
AVDD33_SRV
145
AVDD33_XTAL
AVDD33_XTAL
R200 180K
KEY_5335
152
KEY
ADIN4
151
ADIN3
E
PANEL_SLT
150
ADIN2
SCART_FS_IN
149
ADIN1
PWRDET
148
ADIN0
AVDD33_REG
88
AVDD33_REG
C_XREG
87
C_XREG
ORESET#
71
ORESET_
SW_UPDATE_CTL
72
OPWRSB
DV33
MT5335PKU
D
HDMI_INT
DV33
C
R39
C
4K7
Q1
EDID_PRT
B
BT3904
E
R40
NC\0R
B
DV33
L212
600R
A
8
7
TCM2.0E LA
7.
6
5
CI_PDD3
207
GPIO_3
208
CI_PDD4
GPIO_4
209
CI_PDD5
GPIO_5
59
CI_PDD6
GPIO_6
CI_PDD7
60
GPIO_7
210
CI_POWE#
GPIO_8
CI_OEB
211
GPIO_9
212
CI_ALE
GPIO_10
CI_CLE
214
GPIO_11
215
MT5133_RESET
GPIO_12
216
POWER_ON
GPIO_13
92
OPCTRL0
91
LVDSVDD_EN
OPCTRL1
76
CI_INT
OPCTRL2
75
AMP_MUTE
OPCTRL3
BL_ON/OFF
90
OPCTRL4
89
EDID_PRT
OPCTRL5
DV33
R201
4K7
DV33
CEC
DV33
Z959
T
Z958
T
U205
8
1
R217
VCC
E0/NC
33R
7
2
WC
E1/NC
OSCL0
6
3
Z960
SCL
E2/NC
C
Q206
OSDA0
5
4
B
C124ET
SDA
VSS
M24C16MN
E
T
T
Z957
IIC ADDRESS "A0"
Z956
AVDD33_REG
6
5
33
4
DV33
220R
PWRDET
Adjust the power on timing
R207
10R
C_XREG
DV33
L210
600R
DV33
L211
600R
T
4
3
2
DV33
R211
NC
X200
60M
OXTALI
ORESET#
R208
C
Q202
B
BT3904
E
AVCC_SRV
AVDD33_XTAL
3
2
1
B07
F
TXC
L214
0.82UH
OXTALO
E
D
C
B
A
I_17950_027.eps
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