Table of Contents
Advertisement
KBR0, KBR1, KBR2
KBC0, KBC1, KBC2
to Keyboard
BKLT_EN
to Display
DP_EN_L
SIMPD0
V2
LS1_IN
LS2_IN
SIM_TX
BATT_THERM_AD
SIM_RX
U905
IrDA_EN
VIB_EN
EXT_CHG_EN
HEAD_INT_L
CLK_SELCT
TX_EN
DM_CS
TX_KEY
RX_EN
RX_ACQ
RESET
( SDTX ) BDX
( TX_CLK ) BCLKX
from / to MAGIC
BCLKR
( SDFS ) BFSR
( SDRX ) BDR
15 PIN EXT CONN.
J 600
DSC_EN
13
7
RS232_RX
6
RS232_TX
4
BATT_FDBK
from Charger
8
EXT_CHG_EN
14
EXT_B+
EXT_B+
5
MAN_TEST_AD
1
GND
DSC_EN_AD
3
GND
DOWNLINL_AD
BATT_THERM_AD
10
GND
ISENSE
15
GND
9
ON / OFF
RESET
11
UPLINK
12
DOWNLINK
MIC
2
1
U902
J504
V2
HEADSET
CON.
R976
HEAD_INT_L
R977
VDDS
H2, H1, H3
C14, F10, G4, H4, K5, P13
VCC_MEMIF
J5, J3, J2
KEYPAD
VDD
A9, A10, C5, K6, K10, M8, M11
K3
DISPLAY
VCCA
WHITE_CAP
A11
INTERFACE
SPI
INTERFACE
A4
E9
SIM
E7
INTER
M
F3
U800
B5
E
FACE
M
B2
O
K1
R
C2
Y
A1
N3
A1
C1
I
C1
E2
CPU
N
CTM
E2
E1
C9
T
E1
MODULE
E3
E
E10
E3
E4
R
E4
B11
P2
F
P2
A
C
D9
B6
E
B9
SERIAL
B3
INTER
DSP
B4
F1
FACE
CTM
D4
A3
H5
BATT_SER_DATA
PB6
DSC
K2
L7
CHARGE
L6
BATT_FDBK
UART
to J600
A5
SPI
TIMER
INTERF.
INTERFACE
A6
B7
P4
H10
EXT_B+
MIDRATE_1
MIDRATE_2
ISENSE
F5
A7 B7
D9
C7
CHARGE
D6
SPI
SELECT F10
REAL TIME
INTERFACE
CLOCK
SENSE
U900
A1
LEVEL
B2
SENSE
SHIFT
A2
G_CAP2
B3
CNTL.
D9
ON_2
G5
C4
Logic Control
D2
C2
J2
Interface
Audio
K1
E18
Codec
VBOOST1
A5
REG.
H9
H6 H7 K9
J9
K6
E1
SR_VCC
SPKR
4
1-3
5-8
Q938
L901
ALRT
ALRT_VCC
B+
V2
V3
MAGIC SPI
ADDRESS BUS
DATA BUS
SR_VCC
D6, E1
CE2
B2
U702
CE3
A1
SRAM
R_W
G5
BATT CON.
For description of Midrate Charger
STBY_DL
J604
see document on: emeacs.fle.css.mot.com
4
B+
CHRG_EN
BATT+
4
3
2
Q902
CR903
1,2,5,6
1-3
4
6-8
Q905
Q901
4
3
4,6
2
2
4
Q909
Q904
5
3
7,8
R913
Q900
4
CHRGC
E8
MAIN_FET
F7
BATT+
EXT_B+
D10
CLK
F6
1
J803
RESET
SIM
J7
2
Con.
SIM_I/O
J8
6
4
3
VSIM1
K7
LS1_IN
G6
LS2_IN
K10
SIM_TX
H8
SIM_RX
C8
PWR_SW
G4
STBY_DL
G9
VREF
VREF
2.775V,for Magic
REG.
B5
V3
V3
1,8V, for WhiteCap
REG.
J5
V2
V2
2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM
REG.
A6
V1
V1
5.0V, for DSC Bus, Negative Voltage Regulator
REG.
VSIM
C6
VSIM1
3.0 or 5.0V, for SIM Card Circuit
REG.
C5, B6
A10, C10
B10
CR902
V_BOOST1
Internal GCap use only (VSIM1, LS_V1)
to Backlight
ALRT_VCC
V2
A4, E1, F5
RESET
B4
U701
EPROM
R_W
EEPROM
B3
CE0
D7
CE1
F8
4
1
GND
U904
1
2
3
V1
U903
2
1
BATT_SER_DATA
BATT_THERM_AD
VREF
STBY_DL
DEEP SLEEP
V1_SW
V1
V2
CIRCUIT
( WhiteCap )
GSM SERVICE SUPPORT GROUP
LEVEL 3 AL Block Diagram
to MAGIC
J902
A0
3
D0-D7
5-12
V1-V5
INT.
C702-C706
DIV.
13
V2
2
RESET
14
GND
R_W
4
DP_EN_L
15
( -10V )
1
-10V
KBR0- KBR4
to WhiteCap
-5V
KBC0-KBC4
KEYPAD
PWR_SW
from G CAP2
BACK
ALERT_VCC
LIGHT
from G CAP2
C
B
BKLT_EN
Q907
from WhiteCap
E
J5001 J5002
VIB_EN
1
U501
4
5
VIBRA CON.
B+
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
30.11.00
Rev. 1.0
Dual Band Taishan
Roger Hong, Pei Yuantao, Luo Yu
Page 2
Advertisement
Table of Contents
