Denon DVD-2200 Service Manual page 55

Dvd audio-video / super audio cd player
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W986416DH (MA: IC104)
W986416DH (MA: IC103)
W986416DH Terminal Function
Pin No.
Pin Name
1, 14, 27
V
CC
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
DQ0-DQ15
45, 47, 48, 50,
51, 53
3, 9, 43, 49
V
Q
CC
6, 12, 46, 52
V
Q
SS
16
WE
17
CAS
18
RAS
19
CS
20, 21
BS0, BS1
23~26, 22
A0-A11
29~35
28, 41, 54
V
SS
36, 40
NC
37
CKE
38
CLK
39, 15
UDQM, LDQM Input/Output mask
V
1
CC
2
DQ0
3
V
Q
CC
4
DQ1
5
DQ2
6
V
Q
SS
7
DQ3
DQ4
8
V
Q
9
CC
DQ5
10
DQ6
11
V
Q
12
SS
DQ7
13
V
14
CC
LDQM
15
16
WE
CAS
17
RAS
18
19
CS
20
BS0
21
BS1
A10/AP
22
A0
23
24
A1
25
A2
26
A3
27
Vcc
Function
Power (+3.3V)
Power for input buffers and logic circuit inside DRAM.
Data Input/Output
Multiplexed pins for data output and input.
Power (+3.3V) for I/O buffer Separated power from VCC, to improve DQ noise immunity.
Ground for I/O buffer
Separated ground from VSS, to improve DQ noise immunity.
Write Enable
Referred to RAS.
Column Address Strobe
Referred to RAS.
Command input. When sampled at the rising edge of the clock RAS, CAS
Row Address Strobe
and WE define the operation to be executed.
Disable or enable the command decoder. When command decoder is
Chip Select
disabled, new command is ignored and previous operation continues.
Select bank to activate during row address latch time, or bank to read/write
Bank Select
during address latch time.
Multiplexed pins for row and column address. Row address: A0-A11.
Address
Column address: A0-A7. A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank selected by BS0, BS1.
Ground
Ground for input buffers and logic circuit inside DRAM.
No Connection
No Connection
CKE controls the clock activation and deactivation. When CKE is low,
Clock Enable
Power Down mode, Suspend mode, or Self Refresh mode is entered.
Clock Inputs
System clock used to sample inputs on the rising edge of clock.
The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled
high in read cycle. In write cycle, sampling DQM high will block the write
operation with zero latency.
54
V
SS
53
DQ15
52
VssQ
51
DQ14
50
DQ13
49
V
Q
CC
48
DQ12
DQ11
47
V
Q
46
SS
DQ10
45
44
DQ9
V
Q
43
CC
42
DQ8
41
V
SS
40
NC
39
UDQM
38
CLK
CKE
37
36
NC
35
A11
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
28
Vss
Description
55
DVD-2200
55

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