Harman Kardon AVR 347/230 Service Manual page 13

harman/kardon
10
Address Bit 0 (I
is the chip select signal in SPI mode.
11 Interrupt (Output ) - The CS42528 will generate an interrupt condition as per the Interrupt Mask register.
INT
See "Interrupts" on page 40 for more details.
12 Reset ( Input ) - The device enters a low power mode and all internal registers are reset to their default
RST
settings when low.
13 Differential Right Channel Analog Input ( Input ) - Signals are presented differentially to the delta-sigma
AINR-
14 modulators via the AINR+/- pins.
AINR+
15 Differential Left Channel Analog Input ( Input ) - Signals are presented differentially to the delta-sigma
AINL+
16 modulators via the AINL+/- pins.
AINL-
17 Quiescent Voltage ( Output ) - Filter connection for internal quiescent reference voltage.
VQ
18 Positive Voltage Reference ( Output ) - Positive reference voltage for the internal sampling circuits.
FILT+
19 Reference Ground ( Input ) - Ground reference for the internal sampling circuits.
REFGND
36,37 Differential Analog Output ( Output ) - The full-scale differential analog output level is specified in the
AOUTA1 +,-
35,34 Analog Characteristics specification table.
AOUTB1 +,-
32,33
AOUTA2 +,-
31,30
AOUTB2 +,-
28,29
AOUTA3 +,-
27,26
AOUTB3 +,-
22,23
AOUTA4 +,-
21,20
AOUTB4 +,-
24 Analog Power ( Input ) - Positive power supply for the analog section.
VA
41
VARX
25 Analog Ground ( Input ) - Ground reference. Should be connected to analog ground.
AGND
40
38 Mute Control ( Output ) - The Mute Control pin outputs high impedance following an initial power-on con-
MUTEC
dition or whenever the PDN bit is set to a '1', forcing the codec into power-down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected "active" state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not manda-
tory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
39 PLL Loop Filter ( Output ) - An RC network should be connected between this pin and ground.
LPFLT
42 S/PDIF Receiver Input/ General Purpose Output ( Input/Output ) - Receiver inputs for S/PDIF encoded
RXP7/GPO7
43 data. The CS42528 has an internal 8:2 multiplexer to select the active receiver port, according to the
RXP6/GPO6
44 Receiver Mode Control 2 register. These pins can also be configured as general purpose output pins,
RXP5/GPO5
45 ADC Overflow indicators or Mute Control outputs according to the RXP/General Purpose Pin Control
RXP4/GPO4
46 registers.
RXP3/GPO3
47
RXP2/GPO2
48
RXP1/GPO1
49 S/PDIF Receiver Input ( Input ) - Dedicated receiver input for S/PDIF encoded data.
RXP0
50 S/PDIF Transmitter Output ( Output ) - S/PDIF encoded data output, mapped directly from one of the
TXP
receiver inputs as indicated by the Receiver Mode Control 2 register.
53 Serial Port Interface Power ( Input ) - Determines the required signal level for the serial port interfaces.
VLS
54 Serial Audio Interface Serial Data Output ( Output ) - Output for two's complement serial audio PCM
SAI_SDOUT
data from the S/PDIF incoming stream. This pin can also be configured to transmit the output of the inter-
nal and external ADCs.
55 Recovered Master Clock ( Output ) - Recovered master clock output from the External Clock Reference
RMCK
(OMCK, pin 59) or the PLL which is locked to the incoming S/PDIF stream or CX_LRCK.
C)/Control Port Chip Select (SPI) (Input ) - AD0 is a chip address pin in I
2
AVR 347/230, AVR 350/230 Semiconductor Pinouts
CS42528
2
C mode; CS
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