Interface Timing; Input Signal Timing Specifications - Akai lct2785ta Service Manual

6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.
Signal
LVDS Receiver Clock
LVDS Receiver Data
Vertical Active Display Term
Horizontal Active Display Term
Note (1) Since this module is operated in DE only mode, Hsync and Vsync input signals should be set to
low logic level. Otherwise, this module would operate abnormally.
(2) Please refer to 5.1 for detail information.
DE
DCLK
DE
DATA
Item
Frequency
Input cycle to
cycle jitter
Setup Time
Hold Time
Frame Rate
Total
Display
Blank
Total
Display
Blank
INPUT SIGNAL TIMING DIAGRAM
T
vd
T
h
T
c
T
hb
Symbol Min. Typ.
1/Tc 60 86
Trcl - -
Tlvsu 600 -
Tlvhd 600 -
Fr 47 50
5
Fr 57 60
6
Tv 770 795
Tvd 768 768
Tvb 2 27
Th 1436 1798
Thd 1366 1366
Thb 70 432
T
v
T
hd
Valid display data (1366 clocks)
48
Max. Unit Note
88 MH
Z
200 ps
- ps
- ps
53 Hz
(2)
63 Hz
888 Th Tv=Tvd+Tvb
768 Th -
120 Th -
1936 Tc Th=Thd+Thb
1366 Tc -
570 Tc -
T
vb
Version 1.0