Block Diagram Of Interface - Akai lct2785ta Service Manual

5.4 BLOCK DIAGRAM OF INTERFACE

TxIN
R0-R7
G0-G7
B0-B7
DE
Host
Graphics
Controller
R0~R7 : Pixel R Data ,
G0~G7 : Pixel G Data ,
B0~B7 : Pixel B Data
DE : Data enable signal
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
PLL
LVDS Transmitter
THC63LVDM83A
(LVDF83A)
,
CNF1
Rx0+
51Ω
100pF
Rx0-
51Ω
51Ω
Rx1+
100pF
Rx1-
51Ω
Rx2+
51Ω
100pF
Rx2-
51Ω
Rx3+
51Ω
100pF
Rx3-
51Ω
CLK+
51Ω
100pF
CLK-
51Ω
LVDS Receiver
THC63LVDF84A
45
RxOUT
R0-R7
G0-G7
B0-B7
DE
DCLK
PLL
Timing
Controller
Version 1.0