Clocking Scheme - Nokia n80 User Manual

RM-91; RM-92
System Module
Discrete power supplies are used to generate 2.8 V to BT, 1.5 V for the camera IO voltage, 2.8 V for the front
camera IO voltage, 1.3 V/1.5 V for the application processor and 18 V for the backlight LEDs. The device
supports both 1.8 V/3 V SIM cards which are powered by VSIM1. VSIM2 is used to enable the regulator used
to supply 3V for the mini-SD card interface.
USB accessories which need power from the device are powered by N2300 / VOUT.
The internal LED driver in N2300 is used in this engine implementation.
System power-up
After inserting the main battery, regulators started by HW are enabled. SW checks, if there is some reason to
keep the power on. If not, the system is set to power off state by watchdog. Power up can be caused by the
following reasons:
• Power key is pressed
• Charger is connected
• RTC alarm occurs
• MBUS wake-up
After that:
• N2200 activates sleep clock and VANA, VDRAM, VIO and VR1 regulators.
• Voltage appearing at N2200 RSTX pin is used for enabling N2300 ASIC.
• N2300 enables VCORE regulator and its internal RC-oscillator (600 kHz).
• VCTCXO regulator is set ON and RF clock (main system clock) is started to produce.
• N2200 will release PURX ~ 16ms after power up is enabled (the RF clock is then stable enough).
• Synchronizing clock (2.4MHz) for N2300 is started to be produced. After PURX is released and two rising
edges of 2.4 MHz synchronous clock have been detected in SMPSClk input N2300 is starting to use that
instead of 600kHz internal RC-oscillator.
• HW start-up procedure has been finalized and the system is up and running. Now it is possible for SW to
switch ON other needed regulators.

Clocking scheme

There are two main clocks in the system: 38.4MHz RF clock produced by VCTCXO in RF section and 32.768 kHz
sleep clock produced by the EM ASIC N2200 with an external crystal.
RF clock is generated only when VCTCXO is powered on by the EM ASIC regulator. Regulator itself is activated
by SleepX signals from both RAP and application processor. When both CPUs are on sleep, RF clock is stopped.
RF clock is used by RAP, which provides (divided) 19.2MHz SysClk further to the application processor. Both
RAP and the application processor have internal PLLs which then create clock signals for other peripheral
devices/interfaces like RS MMC, SIM, CCP, I2C and memories.
32k Sleep Clock is always powered on after startup. Sleep clock is used by RAP and the application processor
for low-power operation.
SMPS Clk is 2.4MHz clock line from RAP to EM ASIC N2300 used for switch mode regulator synchronizing in
active mode. In deep sleep mode, when VCTCXO is off, this signal is set to '0'-state.
BT Clk is 38.4MHz signal from the RF ASIC to the Bluetooth system.
CLK600 is 600KHz signal from EM ASIC N2300 to APE VCORE SMPS. The clock source is internal RC oscillator in
EM ASIC (during the power-up sequence) or RAP SMPS Clk divided by 4 after the power-up sequence.
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