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¡ Semiconductor
(3) External data memory access AC characteristics
Parameter
XTAL1, XTAL2 Oscillator Cycle
ALE Signal Width
Address Setup Time
(to ALE Falling Edge)
Address Hold Time
(from ALE Falling Edge)
RD Signal Width
WR Signal Width
RAM Data Read Time
(from RD Signal Falling Edge)
RAM Data Read Hold Time
(from RD Signal Rising Edge)
Data Bus Floating Time
(from RD Signal Rising Edge)
RAM Data Read Time
(from ALE Signal Falling Edge)
RAM Data Read Time
(from Address Output)
RD/WR Output Time from ALE
Falling Edge
RD/WR Output Time from Address
Output
WR Output Time from Data Output
Time from Data to WR Rising Edge
Data Hold Time
(from WR Rising Edge)
Time from to Address Float RD
Output
Time from RD/WR Rising Edge to
ALE Rising Edge
*1 The variable check is from 0 to 24 MHz when the external check is used.
*2 For 2.2 V
<4 V
CC
PORT 0, ALE, and PSEN connected with 100pF load, other connected with 80pF load
Symbol
t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
RLRL
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
*2
t
AVWL
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
t
WHLH
MSM80C154S/83C154S
V
=2.2 to 6.0V, V
CC
SS
Variable clock from
1 to 24 MHz
Min.
41.7
2t
-40
CLCL
1t
-15
CLCL
1t
-35
CLCL
6t
-100
CLCL
6t
-100
CLCL
—
5t
0
—
2t
—
8t
—
9t
3t
-40
CLCL
3t
3t
-100
CLCL
4t
-70
CLCL
1t
-40
CLCL
7t
-105
CLCL
2t
-50
CLCL
0
1t
1t
-30
CLCL
*2
1t
=0V, Ta=–40°C to +85°C
*1
Unit
Max.
1000
ns
—
ns
—
ns
—
ns
—
ns
—
ns
-105
ns
CLCL
—
ns
-70
ns
CLCL
-100
ns
CLCL
-105
ns
CLCL
+40
ns
CLCL
—
ns
—
ns
—
ns
—
ns
—
ns
+40
CLCL
ns
+100
CLCL
289
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