Aiwa XR-MDK109 Service Manual page 61

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IC, TC9409BF
3 7 63 1515 0
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14, 16
15
17
18
19
20
TE
L 13942296513
21
22
23
24, 42 VDD1, VDD2
25
26
27
28
29
30
31
32
33
34
35
36
37
38
www
39
40
41
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43
44
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Pin Name I/O
VDA1 — ADC power supply.
MICI I Input to MIC input low-pass filter.
LPFO1 O Output from MIC input low-pass filter.
VRA1 — ADC reference voltage.
AIL I Input to LINE input L-ch low-pass filter.
LPFO2 O Output from LINE input L-ch low-pass filter.
VRA2 — ADC reference power supply.
AIR I Input to LINE input R-ch low-pass filter.
LPFO3 O Output from LINE input R-ch low-pass filter.
GNDA1 — ADC ground.
LI I Input to L-ch analog adder. (Open when not used.)
LZ O Zero is detected when L-ch digital is input.
GNDA2 — DAC ground.
AOL, AOR O DAC output L-ch. DAC output R-ch.
VR2 — DAC reference voltage.
VDA2 — DAC power supply.
RZ O Zero is detected when R-ch digital is input.
RI I Input to R-ch analog adder. (Open when not used.)
VDX — Oscillator block power supply.
XI I Terminal where external oscillator is connected. (Any of 256, 384, 5 12 or 768 fs).
XO O Terminal where external oscillator is connected.
GNDX — Oscillator ground.
— Digital power supply.
CKS I Master clock selection. (H: 256/384 fs, L: 512/768 fs).
MCK2 O Oscillator clock divided-by-2 output.
MCK1 O Oscillator clock output.
SDO O Digital audio data output.
BCKO O Bit clock output.
LRCKO O Channel clock output.
SDI I Digital audio data input.
BCKI I Bit clock input.
LRCKI I Channel clock input.
GNDD — Digital ground.
______________
RESET I Reset. (Reset at L).
IFD I Microprocessor I/F data input.
IFS I Microprocessor I/F data shift clock input.
IFL I Microprocessor I/F latch pulse input.
EMP I De-emphasis setting. (De-emphasis filter ON at H).
x ao
EXTO O Expansion output terminal.
y
___________
TEST I Test mode setting. (Fixed to normally H).
i
VDL — Digital power supply for DRAM.
GNDL — Digital ground for DRAM.
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