Aiwa XR-MDK109 Service Manual page 57

QQ
3 7 63 1515 0
Pin No.
69
70 AVDD DAC
71 AGND DAC
72
73
74 AVDD DAC
75
76 AGND DAC
77-79 CLK SEL0-2
80
81
82
83, 84 CLK SEL4, 5
85
86
87
88
89, 90
91
TE
L 13942296513
92
______________ ______________
93 VSYNC/CSYNC
94
95 VID_DAC_CK
96
97
98
99
100
101
102
103
104
105
106
107
108
109 VDD MAX OUT
www
110
111
112
.
113
http://www.xiaoyu163.com
Pin Name I/O
Y OUT O Video signal "Y" OUT.
— Analog power supply (DAC) 3.3V.
— Analog ground.
R REF I Reference resistor input.
V REF I Voltage reference input.
— Analog power supply (DAC) : 3.3V.
C OUT O Video signal "C" out.
— Analog ground.
I Clock selection input.
VSS — Ground.
CLK SEL3 I Clock selection input.
VDD3 — Power supply 3.3V.
I Clock selection input.
AGND PLL — Analog ground.
DA XCK I DA XCK (16.933MHz) input.
AVDD PLL — Analog power supply 3.3V.
DA EMP O DAC-emphasis output.
PGIO5, O6 I/O
PGIO0 I/O Programmable I/O.
PGIO8 I/O
______________ ______________
O VSYNC/CSYNC output.
AVDD PLL — Analog power supply (PLL) 3.3V.
O Video DAC clock.
PROC_CK O Processor clock.
AUD_XCK O Audio XCK.
AGND PLL — Analog ground.
VSS — Ground.
NC — No connection.
______________ ______________
HSYNC O HSYNC output.
VDD3 — Power supply 3.3V.
VCK OUT O VCK out.
VSS — Ground.
GCK I Global clock signal input. (42.3MHz)
VCK I Video clock signal input. (27.0MHz)
GCK OUT O Global clock signal output. (27.0MHz)
DA LRCK O DAC-LRCK output.
— Power supply (VDD MAX) : 5.0V.
DA DATA O DAC-PCM data output.
x ao
DA BCK O DAC-BIT clock output.
y
HD OUT O Micon interface. (Data out)
i
HRDY O Micon interface. (Host ready)
http://www.xiaoyu163.com
8
Q Q
3 6 7 1 3
u163
.
73
2 9 9 4 2 8
Description
1 5 0 5 8 2 9 9 4
m
co
9 9
2 8 9 9