Power On Sequence - Pioneer DJM-700-K Service Manual

1

5.4 POWER ON SEQUENCE

A
Main microcomputer
Power-ON
Main microcomputer
reset cleared
Cut mask
B
Mute ON
Sub microcomputer reset
FPGA reset
C
DSP reset
DAC, SRC, DIT, and
ADC reset
Waiting to clear the
sub microcomputer
D
Sub microcomputer
reset cleared
Waiting to initialize the sub
Begin FL30V power supply
Waiting to clear FPGA
E
and DSP
Initialize main computer
Clear DSP reset
Serial communication
F settings for FPGA
38
1
2
90-pin IC1205 clears reset at H
69-pin IC1205 turns Mute ON at H
73-pin IC1205 resets
sub microcomputer at L
85-pin IC1205 resets FPGA at L
79-pin IC1205 resets DSP at L
81-pin IC1205 clears DAC, SRC,
DIT, and ADC reset at H
*1
Wait time: 51 ms
73-pin IC1205 clears sub
microcomputer reset at H
*2
Wait time: 10 ms
68-pin IC1205 begins supplying
30V power to FL at H
Wait time: 939 ms
(1 sec when combined with 61 ms
above)
79-pin IC1205 clears DSP
reset at H
70-pin IC1205 sets serial
communication receiver to FPGA
at H
2
3
Load FPGA program
FPGA reset cleared
Launch DSP, wait for
FPGA stability
DPRAM check
Sub microcomputer
DPRAM access enabled
Waiting to process the
sub microcomputer
Handshake with the
sub microcomputer
Send mute command to
the sub microcomputer
Reset DAC, SRC, DIT, ADC
Waiting to process the
sub microcomputer
DAC, SRC, DIT, ADC
reset cleared
Mask key information
Waiting for DIT and
DAC stability
Initialize DAC
Acquire key information
A
DJM-700-S
3
4
83-pin IC1205 clears the FPGA
program at H.
Data and clock output at 84- and
86-pin IC1205.
87-pin IC1205 completes correct
*4
loading at L.
85-pin IC1205 clears FPGA reset
at L
Wait time: 100 ms
74-pin IC1205 enables sub
microcomputer DPRAM access
at H
Wait time: 10 ms
*5
81-pin IC1205 resets DAC, SRC,
DIT and ADC at L
Wait time: 10 ms
81-pin IC1205 clears DAC, SRC,
DIT, and ADC reset at H
Wait time: 100 ms
*7
4
*6-1
*6-2