Sony HCD-SR1 Service Manual page 111

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DMB08 BOARD IC301 CXP973064-245R (MECHANISH CONTROLLER)
Pin No. Pin Name
1 EEP SO
2
3 DOCTRL/ISBTEST
4 XRST DSD
5
6 EEP RDY
7 FCS JMP 1
8 FCS JMP 2
9 SENS CD
10
11
12 XCS DVD
13
14 to 21 D0 to D7
22 INIT0 DVD
23 INIT1 DVD
24 SCK DSD
25 XRST DVD
26
TE
L 13942296513
27
28
29
30 COUT CD
31
32 CS ZIVA
33
34 SO ZIVA
35 SCK ZIVA
36 DRVIRQ
37 DRVRDY
38
39
40
41
42
43, 44 SLED A, SLED B
45 JIT OFFSET
46 SDOUT DSD
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47 SDIN DSD
48 READY DSD
49 DATA CD
.
50 CLOK CD
51 XMSLAT
52
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I/O
O Not used
SDEN O Serial data enable signal output to DVD/CD RF amplifier
Digital out on/off control signal output to the digital signal processor
O
"L": digital out off, "H": digital out on
O Reset signal output to the DSD decoder
EEP SI I/O Two-way data bus with the EEPROM
I EEPROM ready signal input from the DVD decoder
O Focus jump 1 signal output to the motor/coil driver
O Focus jump 2 signal output to the motor/coil driver
I Internal status (SENSE) signal input from the digital signal processor
CDSP2 O Clock selection signal output to the digital signal processor
CDSP4 — Not used
O Chip select signal output to the DVD decoder
VSS — Ground terminal (digital system)
I/O Two-way data bus with the DVD decoder
I Interrupt signal input from the DVD decoder
I Interrupt signal input from the DVD decoder
O Serial data transfer clock signal output to the DSD decoder
O Reset signal output to the DVD decoder
SCOR I Subcode sync (S0+S1) detection signal input from the digital signal processor
LAT CD O Serial data latch pulse signal output to the digital signal processor
Laser diode on/off control signal output to the DVD/CD RF amplifier
LD ON O
"L": laser diode off, "H": laser diode on
MIRR I Mirror signal input from the digital signal processor
I Numbers of track counted signal input from the digital signal processor
Detection signal input from limit in switch
INLIM I
when "H"
O Chip select signal output to the DVD system processor
SI ZIVA I Serial data input from the DVD system processor
O Serial data output to the DVD system processor
O Serial data transfer clock signal output to the DVD system processor
O Interrupt request signal output to the DVD system processor
O Ready signal output to the DVD system processor
RST I System reset signal input from the DVD system processor
VSS — Ground terminal (digital system)
XTAL I System clock input terminal (20 MHz)
EXTAL O System clock output terminal (20 MHz)
VDD — Power supply terminal (+3.3V) (digital system)
O Sled motor drive signal output
O Output terminal for offset adjustment of APEO (<z/. pin of DVD decoder)
O Serial data output to the DSD decoder
I Serial data input from the DSD decoder
I Ready signal input from the DSD decoder
x ao
y
O Serial data output to the digital signal processor
i
O Serial data transfer clock signal output to the digital signal processor
O Serial data latch pulse signal output to the DSD decoder
SQSO I Subcode Q data input from the digital signal processor
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8
Q Q
3 6 7 1 3
u163
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HCD-SR1/SR2/SR3
2 9 9 4 2 8
Description
"L": reset
"L": reset
1 5 0 5 8 2 9 9 4
The optical pick-up is inner position
"L": reset
m
"L": ready
co
9 9
2 8 9 9
33