Frequency Synthesizer; Vco Circuit; Pll Circuit - Icom IC-M73 Service Manual

• APC CIRCUIT (RF UNIT)
The APC (Automatic Power Control) circuit stabilizes trans-
mit output power to prevent transmit output power level
change which is caused by load mismatching or heat effect,
etc. The APC circuit also selects transmit output power from
high, middle and low power.
The power detector circuits (D91) detects the transmit output
and converts it into DC voltage, which is in proportion to the
transmit output power level. The detected voltage is applied
to the differential amplifi er (IC50, pin 3). The transmit power
setting voltage "PCON" is also applied to another input ter-
minal (pin 1) as the reference voltage.
The differential amplifi er compares the detected voltage and
reference voltage, and the voltage difference is output from
pin 4. The output voltage controls the bias of the pre-drive
(Q53) and power AMP (Q54) to adjust the gain of them for
stable transmit output power.
The transmit power is set by the changing reference voltage
"PCON" and "TCON/LOW."
• PLL CIRCUITS
PLL IC (RF UNIT; IC1)
7
"UNLK"
3
"PLST"
4
"SCK"
5
"SDATA"
15
X1
16
17
LPF
To the FM IF IC
(MAIN UNIT: IC170, pin 2)
19
Prescaler
Programmable
DATA interface
counter
Reference Phase
counter detector

4-3 FREQUENCY SYNTHESIZER

• VCO CIRCUIT (RF UNIT)
The VCO (Q21, Q22, D20−D22) generates the both of trans-
mit signal and LO signal for the 1st IF conversion. The VCO
output signal is buffer-amplifi ed by Q23 and Q24.
While transmitting, the VCO output signal is applied to the
transmit amplifi er circuit, through the TX/RX switch (D50).
While receiving, the VCO output signal is applied to the 1st
mixer (Q150), through the TX/RX switch (D51) and the BPF
(L26 and C122), to be mixed with the received signal to pro-
duce the 21.7 MHz 1st IF signal.
A portion of the VCO output is applied to the PLL IC (IC1,
pin 19), through the buffer amplifier (Q25) and LPF (L20,
C21 and C22).
• PLL CIRCUIT (RF UNIT)
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL output
frequency is controlled by the divided ratio (N-data) from the
CPU.
The buffer-amplifi ed signal from the LPF (L20, C21 and C22)
is applied to the PLL IC (IC1, pin 16). The applied signal is
divided by the prescaler and programmable counter, accord-
ing to the "SDATA (SDATAO)" signal from the CPU (MAIN
UNIT: IC360, pin 10). The divided signal is phase-compared
with the reference frequency signal, which is divided by ref-
erence counter, at the phase detector.
The phase difference is output from pin 13 as a pulse type
signal after being passed through the charge pump. The
output signal is converted into the DC voltage (lock voltage)
by passed through the loop fi lter (R10, R22, C11, C13 and
C24). The lock voltage is applied to the variable capacitors
(D22) of the VCO (Q21, Q22, D20−D22) and locked to keep
the VCO frequency constant.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the VCO oscillating frequency.
Buffer
LPF
Q25
13 Loop
Charge
pump
filter
Q21, Q22, D20–D22
4 - 3
Buffer
Q24
to the TX/RX switch (D50, D51)
Buffer
Q23
VCO