Hardware Overview - National Instruments NI 6115 User Manual

Hardware Overview

CH0+
+
AI CH0
CH0
Mux
Amplifier
CH0–
–
CH1+
+
AI CH1
CH1
Mux
Amplifier
CH1–
–
CH2+
+
AI CH2
CH2
Mux
Amplifier
CH2–
–
CH3+
+
AI CH3
CH3
Mux
Amplifier
CH3–
–
Calibration
Mux
Trigger
Trigger Level
DACs
PFI / Trigger
Timing
STC Digital I/O (8)
DIO
Digital I/O (8)
MUX
FPGA Digital I/O (8)
DAC0
DAC1
© National Instruments Corporation
This chapter presents an overview of the hardware functions on the
NI 6115/6120. Figures 3-1 and 3-2 provide block diagrams for the NI 6115
and NI 6120, respectively.
Anti- CH0
Aliasing 12-Bit
Filter ADC
Anti- CH1
Aliasing 12-Bit
Filter ADC
Anti- CH2
Aliasing 12-Bit
Filter ADC
Anti- CH3
Aliasing 12-Bit
Filter ADC
Analog
2
Trigger
Circuitry
Analog Input
Trigger
Timing/Control
Counter/
DAQ - STC
Timing I/O
Analog Output
Digital I/O
Timing/Control
AO Control
Data (12)
DAC
Data (32)
FIFO
Calibration
DACs
CH0
12
Data (16)
Latch
CH1
12
Data (16)
Latch
CH2
12
Data (16)
Latch
ADC
FIFO
CH3
12
Data (16)
Latch
AI Control
IRQ
DMA
DMA/IRQ
Bus
Interface
RTSI Bus
Interface
RTSI Bus
Figure 3-1. NI 6115 Block Diagram
3-1
3
Control
Generic
PCI
Mini
Bus
Bus
Data (32) MITE
Interface
Interface
Address/Data
EEPROM
Analog
EEPROM DMA
Input
Control Interface
Control
DAQ-STC
DIO
FPGA
Bus
FIFO
Interface
Analog I/O
DIO
Bus
Output
Control
Control Interface
NI 6115/6120 User Manual