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A
B
Q Q
3 7 6 3 1 5 1 5 0
SCHEMATIC DIAGRAMS - 24
2ND DSP SECTION
DSP_DBDA
DSP_DBCK
(Part-20)
from1stDSP
(Part-23)
toASP
1
U007
BAHDM-0471
+3.3V
BLM18PG121SN1D
VDD_XTAL_3.3V
L3401
TC7WHU04FU(TE12L)
1
8
VD
2
7
3
6
4
5
GND
R3442 1M
2
Q3403
X3401
24.576MHz
16
VDD_DSP_3.3V
15
DBG/AUDIO
14
HS0/SD0
13
HS1/SD1
12
HS2/SD2
11
HS3/SD3
10
DSP_DBDA
9
DSP_DBCK
8
DSPC_RST
T E
7
DSPC_BSY
L
1 3 9 4 2 2 9 6 5 1 3
6
DSPC_IRQ
3
5
DSPC_CS
4
SPC1_CLK
3
SPC1_SIMO
2
SPC1_SOMI
1
GND_ARM
HS0/SD0
HS1/SD1
HS2/SD2
TC74VHC125FT
+3.3V
HS3/SD3
1
14
1G
VCC
2
13
1A
4G
3
12
1Y
4A
4
11
2G
4Y
5
10
2A
3G
6
9
2Y
3A
7
8
GND
3Y
R3480
4.7K
4
FORCE_BTM
DBG/AUDIO
While debuging mode,
SPI bus should be separate
+3.3V
1
20
from other devices.
NC
VCC
DSP2_CS
R3487
330
2
19
A1
OE
DIGSDI
47
3
18
R3489
A2
B1
DIGSDO
R3492
330
4
17
A3
B2
330
DIGCLK
R3498
5
16
A4
B3
DSP2_IRQ
R3506
47
6
15
A5
B4
47
DSP2_BSY
R3508
7
14
A6
B5
DSP2_RST
47
8
13
R3510
A7
B6
DSP2_BTM
R3513
47
9
12
A8
B7
10
11
(Part-20,21)
GND
B8
toDA830
C3447
105Z
NJM2855DL1-33
+5.0V
+5VHD
1
w w w
5
GND_ARM
.
DSP_1.1V
The 3.3 V IO supply must rise before or simultaneously with the 1.1 V core supply.
C
NC
R3405
R3406
3.3K
4.7K
NC
R3412
R3413
R3434
3.3K
100
DSPC_RST
R3435
VDD_2NDIO_3.3V
VDD_2NDCOR_1.1V
C3208
105Z
R3439
3.3K
TC74VHC74FT
R3440
3.3K
1
14
1CLR
VCC
37
2
13
SCP2_MISO/I2C2_SDA
1D
2CLR
38
R3290
SCP2_MOSI
3
12
1CK
2D
39
4
11
SCP2_CLK/I2C2_SCL
220
1PR
2CK
40
5
10
GNDIO
1Q
2PR
C3410
104Z
41
6
9
VDDIO
1Q
2Q
42
C3411
104Z
7
8
VDDC
GND
2Q
43
GND
TP3408
44
DAI3_SCLK/GPIO86
TP3409
45
DAI3_DATA/GPIO84
TP3410
46
DAI3_LRCK/GPIO85
C3416
104Z
47
VDDC
48
GND
TP3412
NC
49
R3446
XTAL_OUT
C3418
104Z
50
VDDPLL
51
GNDPLL
CLK_24.576MHz
52
XTI
TP3458
53
XTO
54
GND
C3420
104Z
55
VDDC
47
ADSP_MCK
R3453
56
DAO1_MLCK/GPIO28
ADSP2_SD0
R3454
47
57
MMZ1608Y601BT
DAO1_D0/GPIO96/HS0
R3455
ADSP2_BCK
L3403
58
DAO1_SCLK1/GPIO117
ADSP2_LRCK
120
47
59
R3456
DAO1_LRCK1/GPIO116
ADSP2_SD1
R3457
47
60
DAO1_D1/GPIO97/HS1
ADSP2_SD2
47
61
R3458
DAO1_D2/GPIO98/HS2
ADSP2_SD3
R3459
47
62
DAO1_D3/GPIO99/HS3
47
ADSP2_SD4
R3460
63
DAO1_D4/GPIO100
ADSP2_SD5
R3461
47
64
DAO1_D5/GPIO101
C3427
104Z
65
1K
VDDC
R3462
66
GND
R3464
1K
C3429
104Z
67
VDDIO
R3465
1K
MMZ1608Y601BT
68
GNDIO
R3466
1K
L3404
69
DAO1_SCLK2
R3467
NC
70
DAO1LRCK2
TP3419
NC
71
R3477
DAO1_D6
R3478
NC
72
DAO1_D7
TP3420
VDD_2NDIO_3.3V
3.3K
R3481
C3434 106K/6.3
R3482
NC
C3435 106K/6.3
NC
R3483
C3436 106K/6.3
R3486 4.7K
DBG/AUDIO
DTC144EE
3.3K
R3488
DSPC_CS
Q3407
R3491
3.3K
SPC1_SOMI
SPC1_SIMO
SPC1_CLK
DSPC_IRQ
DSPC_BSY
C3443 105Z
DSPC_RST
C3444 105Z
47
FORCE_BTM
C3445 105Z
R3515
SPI & Debug
Q3409
+3.3V
3
VDD_DSP_3.3V
I
O
x
a o
y
i
TP3431
VDD_2NDIO_3.3V
Iout < 1.5A
http://www.xiaoyu163.com
D
E
8
145
GND_ARM
Q
Q
3
7
6
3
DAO3_MCLK/GPIO130
DAO3_SCLK1/GPIO125
DAO3_LRCK1/GPIO124
DAO3_D4/GPIO114
DAO3_SCLK2/GPIO127
DAO3_LRCK2/GPIO126
u 1 6 3
.
VDD_2NDCOR_1.1V
C3460 104Z
C3461 104Z
VDD_DSP_3.3V
C3466 104Z
for bypasing high frequency current of power plane
http://www.xiaoyu163.com
TX-NR708/808/1008, TX-NA708/808/1008, HT-RC270, DTR-40.2/50.2, DHC-40.2
F
G
2
4
9
9
SPIflash
TP3405
TP3406
GND_ARM
R3407
R3414
1
CS
Q3401
2
SO
3
EN25Q32A-100HIP
WP
4
GND
GND_ARM
VDD_2NDIO_3.3V
144
R3441
47x4
SD_A4
SD_A4
SPI flash:
143
SD_A5
SST or Nyumonix is possible to use
SD_A5
142
SD_A6
with SPI Master Mode-3(w or w/o PLL)
SD_A6
141
SD_A7
SD_A7
140
GNDIO
139
C3412
104Z
VDDIO
138
C3415
104Z
VDDC
137
GND
136
R3445
47x4
SD_A8
SD_A8
135
SD_A9
SD_A9
134
SD_A11
SD_A11
TP3411
133
SD_A12
SD_A12
132
56
SD_CKE
R3447
SD_CLKEN
131
R3448
33
SD_CLKIN
56
130
R3450
SD_CLK
SD_CLKO
129
GND
128
C3419
104Z
VDDC
127
47
SD_UDQM
R3452
SD_DQM1
126
GND_FS
125
VDD_VG
124
C3422
104Z
VDDC
1
5
1
5
0
8
9
2
123
GND
122
GND
121
C3423
104Z
VDDC
120
C3425
104Z
VDDIO
SD_D0
C3426
119
GNDIO
118
TP3413
SD_D1
117
TP3414
C3457
SD_D2
116
TP3415
115
TP3416
SD_D3
114
SD_D8
SD_D4
TP3417
113
C3431
112
SD_D9
SD_D5
102J
TP3418
111
SD_D6
110
SD_D10
109
DAO3_D0
SD_D7
C3433
SD_LDQM
105Z
SD_WE
SD_CAS
SD_RAS
VDD_2NDCOR_1.1V
SD_SDCS
VDD_2NDIO_3.3V
SD_BA0
SD_BA1
SD_A10
SD_A0
SD_A1
SD_A2
SD_A3
C3441
105Z
106K/6.3
C3442
C3446
105Z
m
c o
H
2
8
9
9
TP3403
TP3404
10K
10K
+3.3V
8
VCC
7
NC
6
SCLK
5
SI
1
2
EE_CS0
3
SCP2_HOLD
4
GND_ARM
5
SCP2_MISO
6
SCP2_CLK
7
SCP2_MOSI
8
SPI Memory Writer
SDRAM I/F
4
9
8
2
9
9
GND_ARM
1
54
VDD
VSS
2
53
SD_D15
DQ0
DQ15
102J
3
52
VDDQ
VSSQ
105Z
4
51
SD_D14
DQ1
DQ14
5
50
C3428
SD_D13
DQ2
DQ13
102J
6
49
VSSQ
VDDQ
7
48
105Z
SD_D12
DQ3
DQ12
C3458
8
47
SD_D11
DQ4
DQ11
9
46
VDDQ
VSSQ
10
45
SD_D10
DQ5
DQ10
11
44
C3432
SD_D9
DQ6
DQ9
12
43
102J
VSSQ
VDDQ
105Z
13
42
SD_D8
DQ7
DQ8
14
41
C3459
VDD
VSS
15
40
LDQM
NC
16
39
SD_UDQM
WE
UDQM
17
38
TP3422
SD_CLK
CAS
CLK
18
37
SD_CKE
RAS
CKE
TP3457
19
36
CS
NC
20
35
SD_A11
BA0
A11
21
34
SD_A9
BA1
A9
22
33
SD_A8
A10
A8
23
32
SD_A7
A0
A7
24
31
SD_A6
A1
A6
25
30
SD_A5
A2
A5
26
29
SD_A4
A3
A4
27
28
VDD
VSS
VDD_2NDSDR_3.3V
SDRAM clock is 150MHz,
so 6ns device should be used.
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