Sharp LC-37AD5E Service Manual page 72

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LC-37AD5E
2.7. ICIC1710 (RH-IXB823WJZZQ)
2.7.1 Pin Connections and short description
Pin No.
Pin Name
1
EXP [7]
2
EXP [6]
3
EXP [5]
4
GND*
5
EXP [3]
6
GND*
7
OFLOUT
8
OSCOUT
9
VCCIO1
10
GNDIO
11
GNDINT
12
PCLK
13
VCCINT
14
GCLR
15
GND*
16
GND*
17
GND*
18
GND*
19
GND*
20
GND*
21
GND*
22
#TMS
23
#TDI
24
#TCK
25
#TDO
26
VSYNC
27
HSYNC
28
GND*
29
GND*
30
DMY_IN
31
VCCIO1
32
GNDIO
33
GND*
34
GND*
35
SCK
36
GND*
37
GND*
38
GND*
39
GND*
40
GND*
41
SEN
42
SDA
43
GND*
44
GND*
45
VCCIO1
46
GNDIO
47
GND*
48
GND*
49
GND*
50
GND*
51
GND*
52
GND*
53
GND*
54
GND*
55
GND*
56
GND*
57
GND*
58
GND*
59
VCCIO2
60
GNDIO
61
GND*
I/O
O
Outport [7] (I2C SEL signal)
O
Outport [6] (Digital circuit reset signal)
O
Outport [5] (Digital circuit power control signal)
Ground
O
Outport [3] (Inverter ON control signal)
Ground
O
OFL signal output
O
OSC signal output
VCC (3.3V)
Ground
ground.
I
Reference clock input
VCC (3.3V)
I
RESET terminal. L: RESET, H: Normal
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
I
Pin for JTAG write (Test Mode Select)
I
Pin for JTAG write (Test Data Input)
I
Pin for JTAG write (Test Clock)
O
Pin for JTAG write (Test Data Input)
I
V sync input (not used)
I
H sync input (not used)
N.C.
N.C
I
Dummy pin for RESET line wiring (no effect on operation)
VCC (3.3V)
Ground.
N.C.
N.C.
I
Microprocessor control bus clock
N.C.
N.C.
N.C.
N.C.
N.C.
I
Microprocessor control bus enable
I
Microprocessor control bus data
N.C.
N.C.
VCC (3.3V)
Ground.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VCC (3.3V)
Ground.
Ground.
Pin Function
5 – 13
Sheet Name
DTI2CSEL
DTM_RESET
DTV_ON
N.C.
BL_ON
N.C.
OFLOUT
OSCOUT
FPGA_VCC
Ground.
Ground.
PCLK
FPGA_VCC
RESET_N
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
FPGA_TMS
FPGA_TDI
FPGA_TCK
FPGA_TDO
V_SYNC
H_SYNC
N.C.
N.C.
RESET_N
FPGA_VCC
Ground.
N.C.
N.C.
SCK
N.C.
N.C.
N.C.
N.C.
N.C.
SDE
SDA
N.C.
N.C.
FPGA_VCC
Ground.
N.C.
N.C
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
FPGA_VCC
Ground.
N.C.

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