Schematic Diagram; Cd Servo Circuit - Panasonic SA-AKX50PH Service Manual

18 Schematic Diagram

18.1. CD Servo Circuit

1 2 3
SCHEMATIC DIAGRAM - 1
A
A CD SERVO CIRCUIT
B
C
CN7001
VCC 1
F 2
E 3
LD 4
LD GND 5
GND 6
A 7
D TO
GND GUARD 8
OPTICAL PICKUP
B 9
UNIT
VREF 10
LPD 11
GND GUARD 12
T- 13
T+ 14
F- 15
F+ 16
E
F
C7335 15 16 17 18 19 20 21 30 22 23
0.1
GND
IC7002
C7334
BA5948FPE2
10V220
DRIVER
GND
G
14 13 12 11 10 9 8 29 7
TP 39 TP 38
TP 37 TP 36
+
+
M7301*
TRAVERSE MOTOR
M7302*
SPLINDLE MOTOR
+7.5V
H
1 2 3
4 5 6
: +B SIGNAL LINE : CD AUDIO INPUT SIGNAL LINE
+3.3V
C7626
0.1
C7203
D7650
6.3V220
MAZ8056GML
C7204
0.1
40
Q7601
B1ADCF000001
LASER DRIVE 39
C7216
680P
38
R7650 C7614
6.3V100 37
5.6
TP 51
C7161
(RF) 0.1
36
C7613 0.1
TP 90
35
C7223
50V4.7
34
TP
50 C7102
(RF) 0.47
33
C7142
3300P
32
31
C7107
0.022
30
29
28
TP 28
(VREF)
27
26
25
24
23
TP 87 22
R7327 R7349
21
1K 18K
24 25 26 27 28
R7329 R7328
1K 10K
C7352
C7339
0.018
0.018
6 5 4 3 2 1
R7323 R7331
6.8K 27K
R7325 R7315
330 3.3K
R7335 100
R7332 1K
4 5 6
7 8 9
C7255
0.1
R7217 C7225
1K 1000P
R7218 C7226
1K 1000P
C7230 R7221
0.1 100
C7217
0.1
C7231
6.3V220
R7211 82K
C7244 0.015
41 42 43 44 45 46 47 48 49 50 51 52 53 54
AVSS2
NC
ARFIN
ARFFB
ARFOUT
ARFDC
RFIN
RFOUT
RFENV
CENV
IC7001
MN6627553PA
AVDD2-2 SERVO PROCESSOR
LD
PD
A
C
B
D
F
E
AVSS2-2
20 19 18 17 16 15 14 13 12 11 10 9 8 7
C7154
0.1
C7155
0.1
7 8 9
85
10 11 12
TP 16 TP 14
TP 19
C7227 18
TP
50V1
C7228
TP 17
50V1
55 56 57 58 59 60
TP 13
+3.3V
+1.5V
DVDD2 61
NTEST2 62
TEST 63
TP 25
SBCK / IPFLAG 64
R7260 TP 12
100
C7253
TX 65
TP 7
MCLK 66
TP 8
MDATA 67
TP 9
MLD 68
R7253
TP 4
10
STATS 69
C7243
TP 31
70
BLKCK
NRST 71
R7254
1K
TP
DVSS2 72
C7166
0.01
X2 73
74 S7201
X1
TP
R7220 RESET
1M
IODVDD2 75
R7214
270 S7202
NSRVMONON 76 CD OPEN
X7201 TP
TP 24
H0H169500013
FLAG0 GIOO 77
78
GI01
GI02 79
DQSY 80
6 5 4 3 2 1
SA-AKX50PH/PN CD SERVO
10 11 12
13 14
A
B
C
CN7002
1
25 LCH OUT
24 A.GND
23 RCH OUT
22 +3.3V
21 SRDATA2(SD)
20 SRDATA1(SD)
19 BCK(MD & SD)
18 LRCK(MD & SD)
17 SRDATA(MD & SD)
16 +3.3V
B
15 LD_SW D
470P TO
14 D.GND
MAIN CIRCUIT
13 IPFLAG(SD)
(CN2002)
12 TX
IN SCHEMATIC
11 MCLK
DIAGRAM - 3
10 MDATA
9 MLD
8 BLKCLK
7 STAT
0.1
6 /RST
5 RESET_SW
4 LOADING
3 CD OPEN SW
E
2 P.GND
3
1 +7.5V
25
2
1
F
G
TP 11
TP 10
CIRCUIT
H
13 14