Denon AVR-2313CI Service Manual page 174

Integrated network av receiver
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LC89058W-E (HDMI : U2205)
Pin Functions
P
n i
N
. o
N
1
RXOUT1
2
3
4
5
6
DGND
7
DV DD
8
9
10
11
DV DD
12
DGND
13
14
AV DD
15
AGND
16
RMCK
17
RBCK
18
DGND
19
DV DD
20
RLRCK
21
RDATA
22
SBCK
23
SLRCK
24
SDIN
36
35 34 33 32 31
DO
37
38
DI
39
CE
40
CL
41
XMODE
42
LC89058W-E
DGND
43
DV DD
44
GPIO0
45
GPIO1
46
GPIO2
47
GPIO3
48
RXOUT2
1
2
3
4
a
m
e
/ I
O
O
RX0-6 input S/PDIF through output pin 1
RX0
I
(pd)
5V withstand voltage TTL input level compatible S/PDIF input pin (connected to GND when RX1 is set)
5
RX1
I(pd)
Co-axial compatible S/PDIF input pin (supported demodulation sampling frequency of up to 96kHz)
RX2
I
(pd)
5V withstand voltage TTL input level compatible S/PDIF input pin (connected to GND when RX1 is set)
5
RX3
I
(pd)
5V withstand voltage TTL input level compatible S/PDIF input pin
5
Digital GND
Digital power supply (3.3V)
RX4
I
(pd)
5V tolerable TTL input level compatible S/PDIF input pin
5
RX5
I
(pd)
5V tolerable TTL input level compatible S/PDIF input pin
5
RX6
I
(pd)
5V tolerable TTL input level compatible S/PDIF input pin
5
Digital power supply (3.3V)
Digital GND
LPF
O
PLL loop filter connection pin
Analog power supply (3.3V)
Analog GND
O
R system clock output pin (VCO, 512fs, XIN)
O/I
R system bit clock I/O pin (64fs)
Digital GND
Digital power supply (3.3V)
O/I
R system LR clock I/O pin (fs)
O
Serial audio data output pin
O
S system bit clock output pin (16fs, 32fs, 64fs, 128fs)
O
S system LR clock output pin (fs/4, fs/2, fs, 2fs)
I
External serial audio data input pin
5
30 29 28 27 26 25
24
23
22
21
20
19
18
17
16
15
14
13
5
6
7
8
9
10
11
12
* : Pull-down resistor internal at no selection
F
u
174
SDIN
SLRCK
SBCK
RDATA
RLRCK
DV DD
DGND
RBCK
RMCK
AGND
AV DD
LPF
n
t c
o i
n

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