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TA-F501ES
Q Q
3 7 6 3 1 5 1 5 0
5-2. BLOCK DIAGRAM – DSP Section –
RDATA
AD-DATA1
MUTE
DPBCK
DPLRCK
INPUT
B
DIR-ERR
SECTION
(Page 15)
XCLM
MCK
XNONAUDIO
X1
25MHz
T E
L
1 3 9 4 2 2 9 6 5 1 3
SYSTEM
MUTING
SWICTH
Q2006, 2007
44
167
168
143
w w w
X2004
5
6
12.5MHz
EEPROM
IC2055
TA-F501ES
DSP
AND GATE
IC2
IC2035
78 DPSIA
DPSOA
64
79 DPSIB
CLOCK
SHIFT
IC2036
89 DPBCK
88
DPLRCK
DPDVBCK 87
16
DIR-ERR
DPDVLRCK 86
94
DPFSCK
MUTING
97
XNONAUDIO
IC2052
D +3.3V
AD0–15
AD0 – AD15
143
XTAL
47, 76, 44, 43, 41, 40
7–10, 13–16,
38–35, 33, 32, 30, 29, 27, 26
29–32, 35–38
142
CLKIN
I/O0–I/O15
1D1–1D8, 2D1–2D8
XWR 35
17
XWE
S-RAM
XRD
39
41
XOE
IC7
A0–A18
1–5·18–28·42–44
A16–18
A0–15
2, 3, 5, 6, 8, 9, 11–14
A16, A17, A18
16, 17, 19, 20, 22, 23
48
1LE
ALE 40
25
2LE
SPICLK 125
MOSI 127
XSF_CE 98
FLIP-FROP
SF_CPU_CE
IC4
SF_DSP_MAS
SPI_MAS 63
DSP_SPICLK
BUFFER
DSP_MISI
IC5
DSP_MISO
MISO 126
DSP_SPIDS
XSPIDS 122
DSP_INT
INT_REQ 15
DSP_RESET
XRESET 121
+1.2V
D +1.2V
REGULATOR
22 21 117 116 118 13
99 12
MAIN SYSTEM CONTROLLER
IC2054 (2/2)
141
DSP +3.3V
133 RST TRG
RESET
x
INITIAL
a o
IC2057
y
RESET
144 XRESET
IC2056
.
i
RESET
DSP +3.3V
IC2051
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D/A CONVERTER
IC2004
AUDIO
BUFFER
3 SDTI
AOUTL
11
IC2002
AOUTR
10
R-CH
2 BICK
AUCOM-DATA
4 LRCK
INPUT
A
AUCOM-CLK
SECTION
5 PDN
PREVOL-LAT
(Page 15)
6 SMUTE
1 XCLM
Q
Q
3
7
6
1Q1 – 1Q8
2Q1 – 2Q8
ADDRESS LATCH
IC6
SERIAL FLASH
IC3
1
CE#
6
SCK
5
SI
2
SO
RELAY
DRIVE
DSP +2.5V
Q5271
IC1
78
153
1
FLASH SI
125
SI
2
FLASH SO
126
SO
u 1 6 3
3
MD2
138
MD2
4
RESET
5
+3.3V
3.3
16
16
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2
4
8
9
9
ELECTRICAL VOLUME
IC1203
HEADPHONE
AMP
20
VRIN
OUT
23
TONE
IC1003
AMP
25
TRIM
IC1202
24
TRIM
16 DATA
13 CLK
17 LAT
3
1
5
1
5
0
8
9
m
• R-CH is omitted due to same as L-CH.
• SIGNAL PATH
c o
: AUDIO (ANALOG)
CNP2013
FOR CHECK
: AUDIO (DIGITAL)
.
2
8
9
9
J1001
R-CH
PHONES
RY1001
D_O1
BCK
AMP
E
LRCK
SECTION
RMCK-2
(Page 17)
MUTE
2
4
9
8
2
9
9
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