Harman Kardon AVR 235 Service Manual page 85

No. Pin Name
31 PDN
CM0
32 CDTO
CAD1
CM1
33 CDTI
SDA
OCKS1
34 CCLK
SCL
OCKS0
35 CSN
CAD0
36 INT0
37 INT1
38 AVDD
39 R
40 VCOM
41 AVSS
42 RX0
43 NC(AVSS)
44 RX1
45 TEST1
46 RX2
47 NC(AVSS)
48 RX3
Note 1. All input pins except internal biased pins should not be left floating.
PIN/FUNCTION (Continued)
I/O
Power-Down Mode Pin
I
When "L", the AK4114 is powered-down and reset.
I Master Clock Operation Mode 0 Pin in Parallel Mode
O Control Data Output Pin in Serial Mode, IIC= "L".
I Chip Address 1 Pin in Serial Mode, IIC= "H".
I Master Clock Operation Mode 1 Pin in Parallel Mode
I Control Data Input Pin in Serial Mode, IIC= "L".
I/O Control Data Pin in Serial Mode, IIC= "H".
I Output Clock Select 1 Pin in Parallel Mode
I Control Data Clock Pin in Serial Mode, IIC= "L"
I Control Data Clock Pin in Serial Mode, IIC= "H"
I Output Clock Select 0 Pin in Parallel Mode
I Chip Select Pin in Serial Mode, IIC="L".
I Chip Address 0 Pin in Serial Mode, IIC= "H".
O Interrupt 0 Pin
O Interrupt 1 Pin
I Analog Power Supply Pin, 3.3V
External Resistor Pin
-
18kΩ +/-1% resistor should be connected to AVSS externally.
Common Voltage Output Pin
-
0.47µF capacitor should be connected to AVSS externally.
I Analog Ground Pin
Receiver Channel 0 Pin (Internal biased pin)
I
This channel is default in serial mode.
No Connect
I
No internal bonding. This pin should be connected to AVSS.
I Receiver Channel 1 Pin (Internal biased pin)
TEST 1 pin.
I
This pin should be connected to AVSS.
I Receiver Channel 2 Pin (Internal biased pin)
No Connect
I
No internal bonding. This pin should be connected to AVSS.
I Receiver Channel 3 Pin (Internal biased pin)
Function