Table of Contents
Advertisement
Introduction
Fundamental Principle
Troubleshooting
Function Test and Alignment Procedure
2-1.1 Formatter Board Block Diagram
DPF2A CONTROL
FPGA CLK
VSYNCZ
HSYNCZ
ACTDATA
TFIELD
OLACT
SYNCVAL
LAMP CONTROL&STATUS
COLOR WHEEL INDEX
FLASH
PROGRAMMING
HEADER
IIC BUS
HITACHI
DOWNLOAD
HEADER
CLKIN
Mechanical Construction
Procedure of Disassembly
Firmware Upgrading Procedure
+5V
+12V
VCC2,VOFFSET,VBIAS
VERSET GENERATION
CONFIG/
SEQUENCE
PROM
VOLTAGE ENABLES
BIAS BIN
BIAS/RESET CONTROL
DMD CONTROL
PBUS2
MENORY CONTROL A
CONTROL
MENORY ADDRESS A(12)
MENORY ADDRESS A(12)
FPGA
MENORY ADDRESS B(12)
MENORY CONTROL B
DMD CONTROL
CWRSTZ
VSYNCZ, RESETZ
MICRO
CONTROLLER
COLOR
WHEEL
ALLEGRO
CONTROL
MOTOR
CONTROL
COLOR WHEEL STATUS
Function of Boards
Specifications
DDC Key-In Procedure
VCC2 (DMD)
VCC2 (ASIC)
VOFFSET
VBIAS
VRESET
CLOCK
OSC
FPGA CLK
DATAPATH
INPUTCLK
DMD CLK
FORMATTER
DPF2A
SDRAM CLK
DMD DATA(0..63)
SDRAM A
SDRAM B
COLOR
WHEEL
DRIVE
2-5
EP757
SERVICE MANUAL
Appendix
RESET ASIC
MBIASRST (16)
DMD
0.7” XGA
DATA(0..63)
Advertisement
Table of Contents
