Sn74Hc08Apw-E05 - Sony DSR-300P Service Manual

IC
SN74HC08APW-E05 (TI)FLAT PACKAGE
SN74HCT08APW-E05
SN74HCT08APW-E20 (TI)FLAT PACKAGE
TC74VHC08FS(EL) (TOSHIBA)FLAT PACKAGE
C-MOS QUAD 2-INPUT AND GATES
—TOP VIEW—
14 13 12 11 10 9
V
DD
GND
1 2 3 4 5 6
SN74HC164APW-E05 (TI)FLAT PACKAGE
C-MOS 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
—TOP VIEW—
V
A 1 DD 14
B 2 13 Q8
Q1 3 12 Q7
Q2 4 11 Q6
Q3 5 10 Q5
Q4 6 9 R
D
7 8
CK
GND
Q1 Q2
3 4
8
CK
1
A
2
D Q D Q D Q
B
R R R
D D D
9
RD
SN74HC175APW-E05 (TI)FLAT PACKAGE
C-MOS QUAD D-TYPE FLIP-FLOPS WITH RESET
—TOP VIEW—
Q4 Q3
Q4 D4 D3
16 15 14 13 12 11
V
DD
Q Q
Q
RD
D D
D D
RD
Q Q
Q
1 2 3 4 5 6
RD Q1 Q2
Q1 D1 D2
9-42
8
A
A
Y = Y
B
B
A B
Y = A • B = +
A B
Y
0 0
0
7
0 1
0
1 0 0
0 : LOW LEVEL
1 1 1
1 : HIGH LEVEL
3
Q1
4
Q2
5
1
A
Q3
D
6
2
B
Q4
10
Q5
8 11
Q6
12
Q7
13
Q8
R
D
9
INPUTS OUTPUTS
R CK A B Q1 Q2 Q8
D
0 x x x 0 0 0 0
1 0 x x Q1o Q2o Q8o
1 1 1 1 Q1n Q7n
0 : LOW LEVEL
1 0 x 0 Q1n Q7n
1 : HIGH LEVEL
1 x 0 0 Q1n Q7n
x
: DON'T CARE
Q3 Q4 Q5 Q6 Q7
5 6 10 11 12 13
D Q D Q D Q D Q D Q
R R R R R
D D D D D
Q3 CK
10 9
RD CK
2
4
Q1
D1 3
0 x
Q1
Q
7
5
RD 1
D2 Q2
6
Q2
1
12
10
D3
Q3
1 0
11
13 Q3
D4
15
Q4
RD 9 14
0 : LOW LEVEL
Q4
Q
1 : HIGH LEVEL
GND
RD
x : DON'T CARE
7 8
1
Q : NO CHANGE
0
Q2
Q
: NO CHANGE
0
SN74HC165ANS (TI)FLAT PACKAGE
SN74HC165ANS-E05
SN74HC165APW-E05 (TI)FLAT PACKAGE
C-MOS SERIAL-OR PARALLEL-INPUT SHIFT REGISTER
—TOP VIEW—
L
S/ 1
IN
CK1 2
IN
E 3
IN
F 4
IN
G 5
IN
H 6
IN
QH
7
OUT
8 GND
INPUTS
S/L CK1+CK2 SI A----------H
0 x x a----------h
1 0
1 1
1 x
1 0 x
x
1 1
0 : LOW LEVEL
1 : HIGH LEVEL
x : DON'T CARE
a-h : LEVEL OF INPUTS A-H
QAo - QHo : LEVEL OF QA-QH BEFORE THE INDICATED INPUT CONDITIONS
WERE ESTABLISHED
A
11
10
S
SI
D QA
1
L
S/
R
2
CK1
15
Q8 CK2
SN74HC244APW-E05 (TI)
SN74HCT244ANS (TI)FLAT PACKAGE
SN74HCT244ANS-E05
SN74HCT244APW-E05 (TI)FLAT PACKAGE
C-MOS BUS BUFFER WITH 3-STATE OUTPUTS
—TOP VIEW—
G2
20 19 18 17
V
DD
Q
D Q
x 0 1
1 1 0
0 0 1
Q
x Q
0
0
1 2 3 4
G1
2 18
4 16
6 14
8 12
11 9
OR
13 7
15 5
17 3
G1 G2
1 19
10
SI
V 16
DD
11
A
15 CK2
IN
12
B
13
C
14 D
IN
14
D
3
E
13 C
IN 4
F
5
G
12 B
IN 6 9
SI
H QH
7
A-H
QH
2
11 A
IN CK1
CK1, CK2
15
CK2
S/
10 SI
IN 1
QH
L
S/
9 QH
OUT
CONTENTS OUTPUT
OPERATION
QA QB----- QH
a b----- h PARALLEL LOAD
x 0 QAo--- QGo
RIGHT SHIFT
x 1 QAo--- QGo
x QAo QBo--- QHo
x QAo QBo--- QHo NO COUNT
x
QAo QBo--- QHo
B C H
12 13 6
9
S S S
QH
D QB D QC D QH
7
QH QH
R R R
16 15 14 13 12 11
A Y =
G
G A
0 0
0 1
GND
x x
5 6 7 8 9 10
0 : LOW LEVEL
1 : HIGH LEVEL
x : DON'T CARE
2 18
HI-Z : HIGH IMPEDANCE
4 16
6 14
8 12
G
1
11 9
13 7
15 5
17 3
G
19
: SERIAL DATA IN
: PARALLEL DATA IN
: CLOCK IN ( )
L
: SHIFT/LOAD IN
QH
: 8th BIT OUT
(COMPLEMENTALY)
A Y
G
Y
0
1
HI-Z
DSR-300/P(J,E)/V2