Cxk58257Ctm-70Ll-T6 - Sony DSR-300P Service Manual

CXK1203AR (SONY)
CXK1203AR-T4
C-MOS DIGITAL LINE MEMORY
—TOP VIEW—
37 NC 24
38 23
NC
39 22
40 21
41 20
V
42 DD 19
43 V 18
DD
44 NC 17
45 16
NC
46 15
NC
47 14
NC
48 NC 13
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO. NO.
1 I D0 13 I PSW7 25
2 I D1 14 I PSW6 26
3 I D2 15 I PSW5 27
4 I D3 16 I PSW4 28
5 I D4 17 I PSW3 29
6 — GND 18 I PSW2 30
7 I D5 19 — V 31
DD
8 I D6 20 I PSW1 32
9 I D7 21 I PSW0 33
10 I D8 22 I PSB2 34
11 I D9 23 I PSB1 35
12 I TINT 24 I PSB0 36
AEN : LINE MEMORY SELECT
CLK : CLOCK
DIN0 - DIN9 : VIDEO DATA INPUT
DOT0 - DOT9 : VIDEO DATA OUTPUT
N/P : NTSC/PAL/SECAM SELECT
OEN : OUTPUT ENABLE
PSB0 - PSB2 : DELAY STEP SELECT (1-BITxN)
PSW0 - PSW7 : DELAY STEP SELECT (8-BITxN)
SCLK : CLOCK EDGE SELECT
TINT : TEST
1 - 5
7 - 11
DIN0
1 LINE MEMORY
BUFF
(1138 x 10-BIT)
DIN9
ADDRESS
COUNTER
13 - 18
20, 21
PSW0
ADDRESS
MULTIPLEXER
PSW7
40
N/P
39
AEN
DSR-300/P(J,E)/V2
PIN
I/O SIGNAL I/O SIGNAL
NO.
OEN
I 37 — NC
O DOT9 38 — NC
O DOT8 39 I AEN
I
O DOT7 40 N/P
I
O DOT6 41 SCLK
I
— GND 42 CLK
—
O DOT5 43 V
DD
—
O DOT4 44 NC
—
O DOT3 45 NC
—
O DOT2 46 NC
—
O DOT1 47 NC
—
O DOT0 48 NC
26 - 29
31 - 36
SMALL DELAY
BUFF
DOT0
CONTROLLER
DOT9
25
OEN
PSB0
22-24
PSB2
42
TIMING CLK
41
CONTROLLER
SCLK
12
TINT
CXK58257CTM-70LL-T6 (SONY)(ACCESS TIME=70 ns)FLAT PACKAGE
C-MOS 256 K (32,768 x 8)-BIT SRAM
—TOP VIEW—
OE
22
IN
A11 23
IN
A9 24
IN
A8 25
IN
A13 26
IN
WE
27
IN
28 V
DD
A14 1
IN
A12 2
IN
A7 3
IN
A6 4
IN
A5 5
IN
A4 6
IN
A3 7
IN
A0 - A14
10
A0
CE
9
A1
I/O1 - I/O8
8
A2
OE
7 11
A3 I/O1
WE
6 12
A4 I/O2
5 13
A5 I/O3
4 15
A6 I/O4
CE
3 16
A7 I/O5
1
25 17
A8 I/O6
0
24 18
A9 I/O7
0
21 19
A10 I/O8
0
23
A11
0 ; LOW LEVEL
2
A12
1 ; HIGH LEVEL
26
A13
x ; DON'T CARE
1
A14
OE WE CE
22 27 20
1
A14
26
A13
DECODER
2
A12
23
A11
24
A9 BUFFER
25
A8
3
A7
4
A6
5
A5
21
A10
6
A4
7
A3
BUFFER
8
A2
DECODER
9
A1
10
A0
22
OE
BUFFER
27
WE
20
CE
GND
: ADDRESS INPUTS
: CHIP ENABLE INPUT
: DATA INPUTS/OUTPUTS
: OUTPUT ENABLE INPUT
: WRITE ENABLE INPUT
OE WE MODE I/O TERMINAL
x x NOT SELECT HIGH IMPEDANCE
1 1 OUTPUT DISABLE HIGH IMPEDANCE
0 1 READ OUTPUT DATA
x 0 WRITE INPUT DATA
ROW
MEMORY
MATRIX
512 x 512
19
I/O8
18
I/O7
17
I/O6
16
I/O GATE
I/O I/O5
COLUMN 15
BUFFER
I/O4
13
I/O3
12
I/O2
11
I/O1
IC
21 A10
IN
CE
20
IN
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
14
13 I/O3
12 I/O2
11 I/O1
10 A0
IN
9 A1
IN
8 A2
IN
9-29