Transmitter Part - LG GD510 Service Manual

3. Technical brief
GD510 Operational Description

3.18. Transmitter part

The GMSK transmitter supports power class 4 for GSM850 and GSM900 as well as power class 1 for
DCS1800 and PCS1900. The digital transmitter architecture is based on a very low power fractional-N
Sigma-Delta synthesizer without any external components (see Figure39). The analog I/Q modulation
data from the baseband is converted to digital, filtered and transformed to polar coordinates. The
phase/frequency signal is further on processed by the Sigma-Delta modulation loop. The output of its
associated VCO is divided by four or two, respectively, and connected via an output buffer to the
appropriate single ended output pin. This configuration ensures minimum noise level. The 8PSK
transmitter supports power class E2 for GSM850 and GSM900 as well as for DCS1800 and PCS1900.
The digital transmitter architecture is based on a polar modulation architecture, where the analog
modulation data (rectangular I/Q coordinates) is converted to digital data stream and is subsequently
transformed to polar coordinates by means of a CORDIC algorithm. The resulting amplitude information
is fed into a digital multiplier for power ramping and level control. The ready processed amplitude signal
is applied to a DAC followed by a low pass filter which reconstructs the analog amplitude information.
The phase signal from the CORDIC is applied to the Sigma-Delta fractional-N modulation loop. The
divided output of its associated VCO is fed to a highly linear amplitude modulator, recombining amplitude
and phase information. The output of the amplitude modulator is connected to a single ended output RF
PGA for digitally setting the wanted transmit power. The PA interface of SMARTi-PM supports direct
control of standard dual mode power amplifiers (PA's) which usually have a power control input VAPC
and an optional bias
control pin VBIAS for efficiency enhancement. In GMSK mode, the PA is in saturated high efficiency
mode and is controlled via its VAPC pin directly by the baseband ramping DAC. In this way both up- /
down-ramping and output power level are set. In 8PSK mode, the ramping functionality is assured by an
on-chip ramping generator, whereas output power is controlled by the PGA's as described above.
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Figure 27 Transmitter part block diagram
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