Memory - LG GD510 Service Manual

3. Technical brief
GD510 Operational Description

3.6. Memory

2Gbit NAND & 1Gbit DDRSDRAM employed on GD510 with 8 & 16 bit parallel data bus thru ADD(0)
~ ADD(29). The 2Gbit Nand Flash memory with DDRAM stacked device family offers multiple
high-performance solutions.
ADD[16]
D4
ADD[16:29]
A0
ADD[17]
E4
A1
ADD[18]
F4
A2
ADD[19]
G4
A3
ADD[20]
G8
A4
ADD[21]
F8
A5
ADD[22]
E8
A6
ADD[23]
D8
A7
ADD[24]
D9
A8
ADD[25]
G7
A9
ADD[26]
G5
A10
ADD[27]
F7
A11
ADD[28]
E7
A12
ADD[29]
E9
A13
ADD[0]
L4
ADD[0:15]
DQ0
ADD[1]
M4
DQ1
ADD[2]
N4
DQ2
ADD[3]
L5
DQ3
ADD[4]
M5
DQ4
ADD[5]
N5
DQ5
ADD[6]
M6
DQ6
ADD[7]
N6
DQ7
ADD[8]
M7
DQ8
ADD[9]
N7
DQ9
ADD[10]
L8
DQ10
ADD[11]
M8
DQ11
ADD[12]
N8
DQ12
ADD[13]
L9
DQ13
ADD[14]
M9
DQ14
ADD[15]
N9
DQ15
K6
_BC0
LDQM
K7
_BC1
UDQM
L6
LDQS
LDQS
L7
UDQS
UDQS
C6
SDCLKI _CLK
C7
SDCLKO
CLK
D7
CKE
CKE
TP206
E5
BA0
BA0
TP201
F5
BA1
BA1
TP
F6
_RAS
_RAS
TP
E6
_CAS
_CAS
D6
_WR
_WED
TP205
D5
_RAM_CS _CS
TP
LG Electronics
LGE Internal Use Only
Large Block Memory
(2048Mbit NAND / 1024 Mbit DDR SDRAM, 1.8V I/O)
U201
K522H1HACB-B060
Figure 9 Flash memory & DDR RAM MCP circuit diagram
I_O0
I_O1
I_O2
I_O3
I_O4
I_O5
I_O6
I_O7
I_O8
I_O9
I_O10
I_O11
I_O12
I_O13
I_O14
I_O15
_CE
_WEN
_RE
ALE
CLE
R__B
_WP
VCCN1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSSQ
VDD1
VDD2
VDD3
VDDQ1
VDDQ2
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Revision A
DATA[0]
P10
DATA[0:15]
DATA[1]
N10
DATA[2]
M10
DATA[3]
L10
DATA[4]
F10
DATA[5]
E10
DATA[6]
D10
DATA[7]
C10
DATA[8]
N11
DATA[9]
M11
DATA[10]
L11
DATA[11]
K11
DATA[12] SD_1V8
G11
DATA[13]
F11
DATA[14]
E11
DATA[15]
D11
TP204
G3
_NAND_CS
TP203
M3
_WR
TP202 TP
F3
_RD
TP
L3
ADD[16]
TP
K3
ADD[17]
E3
N3
SD_1V8
H2
C5
C9
G2
H10
P7
SD_1V8
P9
P5
C4
C8
P6
P4
P8
LGE Property
Only for training and service purposes
FCDP
_WP