Lo2 (Pll Loop); Car; Dds Circuit Configuration - Kenwood TK-80 Service Manual

2-3. LO2 (PLL loop)

The part oscillated by X502 and Q517 is output to LO1
cancel loop after passing through the Q518 buffer and input
into mixer IC505. The other part is output from CN502 as
LO2.

2-4. CAR

A digital signal is generated near 695kHz at IC501, and the
analog signal converted by the CP502, CP503 ladder resis-
tors and Q522 D/A converter are mixed with the 10MHz gen-
erated from the chop output of IC501 at IC506. This is then
output as 10.695MHz through the band-pass filter and the
amplifier.
During receiving AM mode, the DDS oscillation is
stopped. In FSK mode, the internal register of IC501 is
switched for direct FSK modulation by the external RTK sig-
nal during selective call mode code transmission by the ABSL
signal from the CPU.

2-5. DDS circuit configuration

The DDS IC has been developed with standard cells to
implement a high-speed circuit and large-capacity ROM at
low cost.
OPTION
SO-2
Q525 Q526
2SC2714(Y) 2SC2714(Y) 2SC2996(Y)
OSC
20MHz
Q529 Q528
2SC2712(Y) 2SC2996(Y)
IC500 Q514
F71022Z 2SC2712(GR)
DDS1
1.195~
1.695MHz
2SC2712(Y)
CHOP
10MHz
DDS2
IC501 Q522
F71022Z 2SC2712(GR)
695kHz+∆
CIRCUIT DESCRIPTION
IC502
Q527
MB86001PF
Rin
DO2
1/40 PD
9
15
N=39~99 1/N
Fin
PLL
6
2SC2714(Y)
IC504
NJM2594V
–
LPF BPF
+
8.305~
8.805MHz 2SC2712(Y)
Q516
Q517
2SC2714(Y)
LPF
OSC
62.35MHz
Q523
2SC2714(Y)
2SC2712(Y)
+
+
LPF
IC506 10.695MHz
NJM2594V
Fig. 2 PLL block diagram and frequency configuration
■ IC configuration
IC configuration is as follows:
• There are two 28 bit registers for setting frequency data,
one 28 bit frequency shift register for addition to the fre-
quency registers, a 23 bit parallel signal input section for
frequency modulation with parallel signals, and a data en-
try and selection section.
• There is a frequency-modulation section comprising 28 bit
adders for adding frequency data and frequency modula-
tion data, a phase data operation section that adds data
from the frequency modulation section and 28 bit phase
data register, and a SIN-ROM that converts phase data to
sine waves.
■ Frequency/shift data setting
Using serial signals synchronized with clock pulses, 30
bits (2 bits that specify the destination for which data is set,
and 28 bits of frequency data) are set in the three internal
registers.
■ Frequency register selection
The data set in the two frequency registers is selected by
the SLAB input of the DDS IC. This pin handles the ABSL
signal for IC501, and the CASL signal for IC500. This function
eliminates the need for the TK-80 to set frequency data for
each transmission/reception with the microprocessor.
Q531,533,535
2SK508NV(K52)
VCO1
Q508~510
2SC3722K(R)
VCO2
A. LPF
VCO3
Q512 IC503
2SC2712(Y) NJM2594V
+
BPF
–
19.5~
Q511
49.5MHz
IC505
UPC1686G
–
BPF
+
Q515 53.545~
54.045MHz
Q519
2SC2714(Y)
Q518
CF500
TK-80
VCO1: 73.145~83.544MHz
VCO2: 83.545~94.544MHz
VCO3: 94.545~103.045MHz
Q536
2SC2714(Y)
LO1
: 73.145~
LPF
Q507
2SC2714(Y)
Q513
2SC2714(Y)
Q520
2SC2714(Y)
LO2
: 62.35MHz
Q521
2SC2714(Y)
Q524
2SC2714(Y)
CAR
: 10.695MHz
103.045MHz
3.4dBm
2.5dBm
–1.2dBm
11