5.6.4 Serial ATA
A Silicon Image Sil3132 device provides two Serial ATA (SATA) ports from the
SBC330, supporting Generation 2 transfer speeds of at 3.0 Gbits/second. The
device is connected to the PEX8518 switch via a x1 PCIe link.
2
2
The SATA device has a dedicated I
C EEPROM (not visible from the processor I
C
interfaces), which can be used to configure registers within the device if required.
The EEPROM is write‐protected by default and can be write‐enabled by clearing
2
the I
C EEPROM Write Protect bit in the Miscellaneous Functions Register.
There are 2 yellow activity LEDs on the rear of the SBC330 to indicate activity on
channels 0 and 1.
5.6.5 General Purpose I/O
The SBC330 supports eight General Purpose digital I/O (GPIO) lines. These are
3.3V single‐ended signals with 5V tolerance. These signals are controlled by the
Local Bus FPGA and can be configured as inputs, with the ability to generate
level‐ or edge‐triggered interrupts, or totem pole outputs that switch to CMOS
TM
levels. The lines are protected via an in‐line IDT QuickSwitch
FET device that
limits any over‐voltages seen by the FPGA. The in‐line FET modifies the
switching characteristic of the lines, from that of the FPGA bi‐directional
transceiver, but testing has shown that switching at up to the local bus speed of
50 MHz is possible.
Each GPIO bit input is protected by quick switch devices, which limit the input
voltage seen by the Local Bus Control FPGA to a safe level. Electrical
characteristics of the GPIO pins can be found in Section A.2.4
.
GPIO lines 0 and 1 (on VPX connector P2 A15 and B15 respectively) are dual
function and are reserved for the use of GEIP's AXIS Multiprocessor Message
Passing software when used. All GPIO registers are in the Local Bus FPGA, and
are defined in Chapter 6 •
.
Publication No. SBC330-0HH/3
Functional Description 37