Fujitsu F2MC-8FX Hardware Manual page 67

Table 6.3-1 Functions of Bits in System Clock Control Register (SYCC)
Bit name
SCM1, SCM0:
bit7
Clock mode monitor
bit6
bits
SCS1, SCS0:
bit5
Clock mode selection
bit4
bits
SRDY:
Subclock oscillation
bit3 stability bit
(Two-system clock
product only)
SUBS:
Subclock oscillation
bit2 stop bit
(Two-system clock
product only)
DIV1, DIV0:
bit1
Machine clock divide
bit0
ratio selection bits
Indicate the current clock mode.
When set to "00": the bits indicate subclock mode.
When set to "10": the bit indicate main clock mode.
When set to "11": the bit indicate main PLL clock mode.
These bits are read-only; any value attempted to be written is meaningless.
Specify the clock mode.
When set to "00": the bits specify transition to subclock mode.(Two-system clock product only)
When set to "01": setting is prohibited.
When set to "10": the bits specify transition to main clock mode.
When set to "11": the bits specify transition to main PLL clock mode.
Once a clock mode has been selected in the SCS1 and SCS0 bits, any attempt to write to them is ignored
until the transition to that clock mode is completed.
On single system clock product, an attempt to write "00" or "01" to these bits is ignored, leaving their
value unchanged.
Indicates whether subclock oscillation has become stable.
• When set to "1", the SRDY bit indicates that the oscillation stabilization wait time for the subclock has
passed.
• When set to "0", the SRDY bit indicates that the clock controller is in the subclock oscillation
stabilization wait state or that subclock oscillation has been stopped.
This bit is read-only; any value attempted to be written is meaningless.
On single system clock product, the value of the bit is meaningless.
Stops subclock oscillation in main clock mode or main PLL clock mode.
When set to "0": the bit enables subclock oscillation.
When set to "1": the bit stops subclock oscillation.
Notes:
• In subclock mode, the subclock oscillates regardless of the value of this bit, except in stop mode.
• Do not update the SYCC: SCS1 bit and this bit at the same time.
• On single system clock product, the value of this bit has no effect on operation.
• These bits select the machine clock divide ratio to the source clock.
The machine clock is generated from the source clock according to the divide ratio set by the
•
bits.
Machine Clock Divide Ratio
DIV1 DIV0
0 0 Source clock (No division)
0 1
1 0
1 1
CHAPTER 6 CLOCK CONTROLLER
Function
Selection Bits
Source clock/4
Source clock/8
Source clock/16
SCM1, 0 = 10
B
Main clock divided by 2
Main clock divided by 8
Main clock divided by 16
Main clock divided by 32
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